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I am trying to build a timing circuit to generate a 0.5 Hz 50% duty cycle signal. In other words 1 second on, 1 second off, and so on...

I have searched a few places and found the following instructions but that did not work. http://electronicsclub.info/555timer.htm#dutycycle.

Any ideas?

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  • \$\begingroup\$ Which of the instructions there did you try, and how, exactly, did it not work? \$\endgroup\$ – Peter Bennett Jun 3 '14 at 0:22
  • \$\begingroup\$ the instruction posted on the link above. Middle of the page, there is a section about 50% duty cycle and a circuit diagram. Using the formula Tm = 0.7 * R1 * C1 and Ts = 0.7 * R2 * C1, I calculated the R1 and R2 to be approx 65K and Capacitance to be 22 UF but I only get 1.5 ms on time which doesnt make sense, and it is to close 5% duty cycle instead of 50%. \$\endgroup\$ – user43916 Jun 3 '14 at 0:28
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    \$\begingroup\$ @user43916 Put your calculation into the body of the question, and tell us what you've got vs. what you were expecting. If you have specific question, ask it. For future reference, "Any ideas?" is not a specific question. Neither "that didn't work" is specific. Turns out that "that" was a calculation that didn't work... Who would have guessed?.. \$\endgroup\$ – Nick Alexeev Jun 3 '14 at 0:43
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    \$\begingroup\$ @user43916 Welcome to EE.SE, by the way. \$\endgroup\$ – Nick Alexeev Jun 3 '14 at 0:44
  • \$\begingroup\$ Hmmm...the site you refer to says the formula is "Tm = 0.7 × (R1 + R2) × C1". The duty cycle becomes closer to 50% as R1 approaches 0. Try R1=1k, R2=150k, C=10uF. \$\endgroup\$ – aja Jun 3 '14 at 12:54

10 Answers 10

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See the description of "Better Timing" in 555 Timer Circuits. That circuit eliminates the classic R2, adds an NPN transistor (2N3904 is fine), a new R2 just to bias the added NPN transistor (i.e. does not participate in the RC circuit), and two diodes to charge and discharge the capacitor through R1. This gives a 50% duty cycle (as the charging and discharging is done through the same, single resistor).

From the linked site:

[Better Timing]

Also from the linked site:

Better and more stable timing output is created with the addition of a transistor and a diode to the R-C timing network. The frequency can be varied over a wide range while maintaining a constant 50% duty-cycle. When the output is high, the transistor is biased into saturation by R2 so that the charging current passes through the transistor and R1 to C. When the output goes low, the discharge transistor (pin 7) cuts off the transistor and discharges the capacitor through R1 and the diode. The high & low periods are equal. The value of the capacitor (C) and the resistor (R1 or potmeter) is not given. It is a mere example of how to do it and the values are pending on the type of application, so choose your own values. The diode can be any small signal diode like the NTE519, 1N4148, 1N914 or 1N3063, but a high conductance Germanium or Schottky type for the diode will minimize the diode voltage drops in the transistor and diode. However, the transistor should have a high beta so that R2 can be large and still cause the transistor to saturate. The transistor can be a TUN (europe), NTE123, 2N3569 and most others.

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It's impossible to get a 50% output from a 555 with the conventional 2 resistor 1 capacitor astable arrangement.

The easiest way is to use a CMOS 555 and to use the circuit shown on the title page of:

http://datasheets.maximintegrated.com/en/ds/ICM7555-ICM7556.pdf

The next easiest way, and the way to achieve any duty cycle from <1% to >99% is to use diode steering around the astable's resistors

The way to get the most accurate 50% is to set the 555 to output twice the frequency you want and then to do a divide-by-two on its output with a "D" type flip-flop.

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enter image description here

enter image description here

In this modified astable multivibrator circuit the forward voltage drop of the diode D1 is always ignored, and the timing formulas are given as

$$ t_1 = \ln(2)R_1C_1, \quad t_2 = \ln(2)R_2C_1. $$

If you take \$R_1 = R_2\$ and ignore the diode voltage drop, you achieve %50 duty cycle. But, what happens if we don't ignore the diode voltage drop?

Suppose that the forward voltage drop of D1 is \$V_D\$. The voltage at pin 5 will be \$\dfrac{2}{3}V_{cc}\$.

The most general form of capacitor charging equation is

$$ v_c(t) = V_s + \left[ v_c(t_0) - V_s \right] e^{-\dfrac{t-t_0}{RC}}, \quad t\ge t_0. $$

If we rearrange the terms to get the time difference, we get

$$ \Delta t = t - t_0 = RC \ln \left[ \dfrac{V_s - v_c(t_0)}{V_s - v_c(t)} \right] . $$

Where, \$v_c(t)\$ is the function of capacitor voltage, \$V_s\$ is the source voltage.

During the on-time, the capacitor C1 will charge from \$\dfrac{1}{3}V_{cc}\$ to \$\dfrac{2}{3}V_{cc}\$ over R1. The supply voltage this R-C network sees is \$V_{cc}-V_D\$.

$$ t_1 = R_1C_1 \ln \left[ \dfrac{V_{cc} - V_D - \dfrac{1}{3}V_{cc}}{V_{cc} - V_D - \dfrac{2}{3}V_{cc}} \right] = R_1C_1 \ln \left[ \dfrac{\dfrac{2}{3}V_{cc} - V_D}{\dfrac{1}{3}V_{cc} - V_D} \right] = R_1C_1 \ln \left[ 1 + \dfrac{V_{cc}}{V_{cc} - 3V_D} \right] $$

During the discharge, D1 has no effect. So, similarly, \$t_2\$ will be

$$ t_2 = R_2C_1 \ln \left[ \dfrac{V_{cc} - \dfrac{1}{3}V_{cc}}{V_{cc} - \dfrac{2}{3}V_{cc}} \right] = \ln(2) R_2C_1. $$

Then the period of the oscillation is

$$ \boxed{T = t_1 + t_2 = R_1C_1 \ln \left[ 1 + \dfrac{V_{cc}}{V_{cc} - 3V_D} \right] + \ln(2) R_2C_1}. $$

And the frequency is

$$ \boxed{f = \dfrac{1}{T} = \dfrac{1}{t_1 + t_2} = \dfrac{1}{R_1C_1 \ln \left[ 1 + \dfrac{V_{cc}}{V_{cc} - 3V_D} \right] + \ln(2) R_2C_1}}. $$

(Adapted from this question.)


Compensation of The Error Due To Diode Forward Voltage Drop

We want to make the on and off times are equal. That is

$$ t_1 = t_2. $$

Then,

$$ R_1C_1 \ln \left[ 1 + \dfrac{V_{cc}}{V_{cc} - 3V_D} \right] = \ln(2) R_2C_1,\\ \ln \left[ 1 + \dfrac{V_{cc}}{V_{cc} - 3V_D} \right] = \dfrac{R_2}{R_1} \ln(2),\\ \boxed{R_1 = R_2 \dfrac{\ln(2)}{\ln \left[ 1 + \dfrac{V_{cc}}{V_{cc} - 3V_D} \right]} \quad\quad \text{or} \quad\quad R_2 = R_1 \dfrac{\ln \left[ 1 + \dfrac{V_{cc}}{V_{cc} - 3V_D} \right]}{\ln(2)}}. $$

You have to choose \$R_1\$ and \$R_2\$ proportional to each other like this in order to achieve precisely symmetrical 50% duty cycle.

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  • \$\begingroup\$ Why is it impossible to have 50% duty cycle? You can always chose R2 < R1 to compensate for the voltage drop on the diode, right? \$\endgroup\$ – Dmitry Grigoryev Jun 22 '15 at 11:34
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Do this with a cheap and small microcontroller, like the PIC 10F200. That only requires two parts, the micro, which is available in a SOT-23 package, and the bypass cap.

Then get a 666 555 timer from your favorite museum gift shop and glue it over the PIC and cap to show the world that it's done with a 555 timer. Those that don't look too hard will be scratching their heads how you got the accuracy so high, and the drift and power consumption so low.

For extra credit, add a few more parts to really make them scratch their heads. The museum gift shop will certainly have 741 opamps too. Get the ones in a can for the best nostalgic look.

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Your calculations are wrong, but not that wrong. Using equal 65k resistors should give you a 33% duty cycle (t1 = .7 R1 C, t2 = .7 (R1 + R2) C). Your computations were carried out correctly given that your formulas were wrong, and the values you used should give a total period of 3 seconds rather than two. The change in duty cycle suggests that you've either got one of your resistor values wrong (and you need to measure them), or you wired the chip wrong. Your overall timing suggests that your capacitor is way off. I suggest that you're using a 22 nF capacitor rather than a 22 uF.

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Using this calculator, I was abler to compute the following values:

R1 = 1K
R2 = 360K
C1 = 4 µF

Frequency = 0.5 Hz
Period = 1.999s
50.07% duty cycle
1.001s on, 997.2 ms off

which is pretty much spot on. However 360K is not as standard resistor value; the closest is 357K. This gives:

R1 = 1K
R2 = 357K
C1 = 4 µF

Frequency = 0.505 Hz
Period = 1.982s
50.07% duty cycle
992.37 ms on, 989.6 ms off

However worrying about the difference caused by the 3K is pretty much irrelevant, because you have to take into consideration the tolerance of the components. Assuming you are using 1% resistors, changing the value of R1 by 1% has little effect, and changing the value of R2 by 1% is about the change from 350K to 357K shown above.

The problem is the capacitor C1. Many capacitors have a tolerance of ±20%. This means the 4 µF cap could vary from 3.2 µF to 4.8 µF which will cause the period to vary from 1.586 s to 2.378 s. Luckily this can be compensated by changing R2; 3.2 µF along with R2 = 450K reverts to the original timing shown above, as does 4.8 µF along with R2 = 300K. So bottom line, once you pick a capacitor, you are going to have to adjust R2 to give you the period you need.

I suggest using a 500K pot for R2 to start with, adjust until you get the required period, then measure the setting of the pot and replace it by a fixed resistor.

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Follow this image:

555 astable

Choose R1=R2 and put a diode in parallel with R2, with cathode facing capacitor C.

T1 will be= 0.693 x R1 x C

T2 will be= 0.693 x R2 x C

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enter image description here

Keeping both charging and discharging time of capacitor equal . Getting around 0.49 - 0.5 Hz with 50% duty cycle .

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Before designing more complex things please take a look page 16 http://www.ti.com/lit/ds/symlink/lmc555.pdf enter image description here

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I built the circuit in question in this thread using the 555 in the astable mode which included using a 1uf cap for C1, R1 was 100k, R2 was 1Meg, no cap at pin 5 (control voltage), no diode across R2 as suggested to lower the duty cycle. The results were a 53% duty cylce at .5 Hz (Or very close to it). Supply voltage was 12vdc but there was an 8 volt overshoot on rise that was 12 microseconds in duration, so I added a .01uf ceramic disc cap across output pin 3 and ground, it created a very slight charge curve at the top but eliminated the spike, this was expected. I used this to control another circuit I built that uses another 555 and an LM339 (or LM393) op amp. It uses a 1 Meg pot connected to pins 2 & 6 (between - and + on the supply voltage with the wiper connected to pins 2 & 6 on the second 555) this was to be able to adjust the frequency on the second 555 (output pins 3 & 5 were not used in the second circuit), then I used a 50k pot at the negative input of the op amp to adjust the duty cycle. The wiper of this pot connected to the negative side of the op amp. The positive input of the op amp came from pin 7 on the second 555. Note, you can raise the value of R2 or lower the value of R1 to increase the duty cycle (on the first 555 being discussed in this thread).

End result for final output was "off for close to 1/2 second, then oscillated at 4 hZ while "on" or in the "high" state. I used only one output from the op amp. I used an NMOS for output of the op amp to be "on" while output was high, then used a PMOS for an "on" output while in the low state. This create an alternating output from just one op amp output for approximately 1/2 second (Based on the frequency and duty cycle of the first 555), then off for approximately 1/2 second. I am able to adjust the duty cycle and frequency at will but the first 555 is fixed at a 53% duty cycle at .5 Hz The second circuit with the second 555 and an op amp will produce 188 kHz, I was quite surprised that it would go that high, I was expecting about 125 kHz at best. The waveforms are pretty much pointed rather than anything resembling a square wave but it works. Anything higher than 188 kHz was too much, the 555 wouldn't cycle any faster than that. The MOSFETS and op amp could handle it but not the 555 that I used (NE555N) At least that was my conclusion based on the process of elimination and further testing with various resistors and caps. I use the second circuit as a variable frequency and variable duty cycle driver to test new designs for other circuits. It uses a 470nf cap for full potential on the high end of the frequency and a 47nf cap for the low end. It will adjust from .3 to 99% duty cycle and from .3 Hz to 188 kHz.
Hope this helps someone else. I can send the circuit diagram to anyone who wants it or I can post a link to it if there's an interest. Final note, this combined circuit only draws 56mA with a 36mA load (56 mAh average). I used a data logger over a 10 minute span at 1 second intervals for the sample rate, then downloaded it onto an EXCEL spreadsheet for analysis.

I used to design circuits twenty years ago but things have changed a lot since then so I'm having to learn many new devices from scratch. So, If I've made any mistakes in explaining this, please feel free to point them out!! :-)

Thanks!!!

Joe

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  • \$\begingroup\$ Please post a link to the circuit diagram or, better yet, edit your answer so it'll incorporate the schematic itself. \$\endgroup\$ – EM Fields Nov 9 '14 at 21:26

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