I have attached a circuit which includes three counters which are the IC 74163. This specific IC is a 4 bit counter. I want to make a bigger counter which will be able to count 752 steps with an input frequency of 20 MHz. The fact is that my counter does not work at all and I would like to know what do I make a wrong. Is there something that I do not see? In this case the preset is 4095 - 1 - 752 (steps) = 110100001110. Unfortunately the system does not count correctly and I am sure that there something wrong with my design. Could please someone give me advice?
The input signal is 26.6 kHz and the frequency of the system is 20 MHz. Also the reason for doing something like that is because I am trying to use an external PLL in cooperation with my FPGA design and the circuit below is used to make the division which is needed fout = N * fin and theoretically I want to make a division of 752 so I need 752 steps. The system does not work well but with another preset value it worked. Despite the fact that I get the 20 MHz I need digitally I want to understand completely why the counter that I have designed does not work properly.
The reason for which I do not get a bigger counter is that I have to simulate the system using parts available from my FPGA's software library. Is there a possibility of overflow or something like that, which I cannot see?