# Virtex 4 fx 12 ff668

Could anyone explain me how I can use DCM of Virtex 4 fpga to get divided clock-50MHz of the system clock-100MHz?

In UG070v2.6 (the V4 userguide), see Fig 2-8: Standard Usage but use CLKDV instead of CLK0 as the output. Make sure the Divide by Value is set to 2.