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Could anyone explain me how I can use DCM of Virtex 4 fpga to get divided clock-50MHz of the system clock-100MHz?

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In UG070v2.6 (the V4 userguide), see Fig 2-8: Standard Usage but use CLKDV instead of CLK0 as the output. Make sure the Divide by Value is set to 2.

Or use the Clocking Wizard in Coregen to walk you through the options and generate you an HDL file.

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