I'm a connecting a WOL interrupt port of the PHY (an open drain port) to the ON-OFF port of the PMIC of my device. The idea is do a reset of the PMIC and then I'm going to turn on the MCU from a completly off state (not sleeping or any thing like that).
The PMIC ON-OFF pin is configured to detect levels, is always pulled up to a always +3V3 [V] so if the open drain is asserted, that would shutdown the PMIC. BUT according to the ethernet PHY, when an WOL (WakeOnLan) event occurs, a register in the PHY is gonna go to 1 and the only way to deassert the signal would be changing that register to 0 (its default state) trough I2C in the PHY, so like we don't have logic on all the time would be asserted that signal so the PMIC will continue off.
But I'm thinking that if a take to 0 the ON-OFF signal of the PMIC that will kill the power of the phy so the phy wound't be able to mantaing that open drain signal asserted and then the PMIC will turn on and the PHY will start in its default state (that register in 0).
What do you think about that? Please can give some feedback.
info: The PHY datasheet: http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf
PMIC datasheet: https://www.dropbox.com/s/9jjrwr8acowj2zo/MMPF0100.pdf