Is it possible to move VHDL code from the top level of a design to a subcomponent, without changing the underlying logic?

Question

Suppose I have a component, called Top_Level, that has a bunch of registers that it uses. There are some subcomponents that perform some combinational logic using the registers. There is also a clocked process, Process_1, that does sequential operations on the registers. So, every clock cycle, Process_1 does some sequential stuff with the registers. Then, the subcomponents in Top_Level do their combinational logic.

Process_1 is getting kind of big, so I'd like to make it a subcomponent of Top_Level called Component_1. Here's the problem: to make Process_1 a subcomponent of Top_Level I have to move all of the registers that it uses down to the new Component_1. But then the other subcomponents in Top_Level wouldn't be able to access those registers.

Is there a way to get the registers of Component_1 to also act as outputs of Component_1? Then I could copy/paste my code into Component_1 without having to rename all of my registers and signals.

Answer 1

Yes, and it is actually a good practice. It seems like you have already answered most of your own question: turn the registered values into outputs of the lower-level component. This should get you on the right path; if you need more details on how to do that, please show us your source code.

Some other hints that might be helpful:

• In VHDL-2008, you can read from output ports, so you don't have to rename your existing signals. In previous VHDL versions, you could use buffer mode ports to the same effect.

• IDEs with integrated refactoring (like Sigasi) can rename signals for you automatically, so this is actually less work than it seems.

Answer 2

If your concern is about reading outputs from inside the entity, you just have use a regular signal for the desired internal feedback, and also assign it to the output port. This way, you are not directly reading the output label, which is the language's limitation. The following code should make this clearer:

entity e is
port(
    clk   : in  std_logic,
    myin  : in  std_logic,
    myout : out std_logic
);
end entity;

architecture a of e is

signal result : std_logic; -- Becomes your output, and can be used for internal feedback.

function mylogic(a : std_logic; b : std_logic) return std_logic is
    variable ret : std_logic := 0;
begin
    -- assign ret using 'a' and 'b'...
    return ret;
end function;

begin

myout <= result;

process(clk)
begin
    if rising_edge(clk) then
        result <= mylogic(myin,result);
    end if;
end process;

end architecture;

In the above, myout is the same as result, which is used internally. By doing this, you are not duplicating your registers - it is the same physical signal, and no extra resources are required.