In order to drive pass transistors (MOSFETs) located between two non-zero voltage points, one can use a resistor divider followed by a MOSFET as seen here where V2 is high enough to drive the top MOSFET:


simulate this circuit – Schematic created using CircuitLab

This works, but I hardly think it's ideal. This has the drawback of taking time to turn on and off as you now have a potentially hefty RC time constants between the R's and the capacitance of the top NMOS. To counter that slowness, you could burn more current during the off time by reducing the resistances. Either way, there's a balance that must be had that may not be anywhere near ideal.

Is there a better way drive a pass transistor at some very different voltage than the driving signal (0-5V). I can see opto-isolators working for this. There would obviously be pros and cons to each of these options. Anything better?

Also, assume that the mosfets have between 10-20V max \$V_{GS}\$ and can have very high (200-400V) max \$V_{DS}\$. Equivalent PMOS devices could be used as well if using some kind of complementary logic.

EDIT: Changed V2 to V1+Vt and added notation for the schematic to have Q1 and Q2.

Andy has pointed to some chips with internal capabilities to do what I'm after. My question is, what's in level shifters or buffer elements of the datasheet he gave. Here's the block diagram of the LTC4444:

enter image description here

  • \$\begingroup\$ A schematic with complete ref designators would be really helpful. \$\endgroup\$ – gsills Jun 6 '14 at 22:27

With the circuit you've shown and if it's used as a slow switch such as turning power on or off from a battery or load then you can manufacture a higher voltage rail above the power rail and use a simple driver - power wasted with slow turn on and turn off time is important but not as important as when driving a PWM signal thru a H bridge.

For this there are a plethora of devices that can be used that steal a little power from the output to manufacture a higher voltage rail and this can easily provide enough spare juice to have a really efficient push-pull driver that turns the power mosfet on and off very effectively and at high speed.

There are several devices that work with an input logic referenced to 0V whilst the output push-pull driver is over 100 volts higher. Off the top of my head the Linear technology LTC4444 falls into this category but if I've got the number wrong I'll correct it shortly. No it's fine: -

enter image description here

In my opinion, it's still more efficient to use an N channel FET driven this way as the "top" transistor compared to the relative simplicity of using a slightly less power-efficient P channel FET.

EDIT - as for the high-side driver consider this circuit from here: -

enter image description here

  • \$\begingroup\$ Just to clarify, you're saying that circuit shown in the question is a good circuit for the purpose so long as I don't need speed. You're just describing a way to obtain a good V2, right? \$\endgroup\$ – horta Jun 6 '14 at 21:27
  • \$\begingroup\$ @horta The circuit doesn't show how the top FET is driven but if it did (how I envisage it) then it's ok for slow stuff. Look at the LTC4444 - I've embedded a picture now - this device and others like it are really good at obtaining "V2" and hard driving both top and bottom FETs. Everyone (probably without exception) who manufacture buck converters have this technology available and this is used on all the power high speed switchers - just look at LT's range - note the BOOST pin (others call it bootstrap). That's the clue to what is happening. \$\endgroup\$ – Andy aka Jun 6 '14 at 21:48
  • \$\begingroup\$ I get that I can bootstrap stuff and get V2 (V1+Vt) through boost converters or charge pumps or some other manner, but my question isn't really after how to get V2. Placing it as a signal I thought implied that I already had that. Now the LTC4444 circuit is interesting, but what I'm really asking is what is in the "high side level shifter" in the "Block Diagram" of that datasheet. \$\endgroup\$ – horta Jun 7 '14 at 0:04
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    \$\begingroup\$ @horta look at figure 23 in this document ti.com/lit/ml/slup169/slup169.pdf - this is one method but there are others and my personal favourite bootstraps the PWM signal via a capacitor. \$\endgroup\$ – Andy aka Jun 7 '14 at 10:06
  • \$\begingroup\$ Awesome! That's what I was after. Thank you for multiple solutions and sticking with me through my poorly worded question. \$\endgroup\$ – horta Jun 9 '14 at 14:03

This really isn't a switching circuit. What happens if there is voltage at V1 and V2? Q1 will conduct, since this is just a source follower. Voltage at V2 will put voltage on the gate of Q1 (Vg), and the source will be Vg-Vt. If you are trying to switch off Q1 this circuit won't work since source voltage (Vs) just follows Vg-Vt and will not turn off until Vs is constrained by some voltage from the load or ground. If you are trying to end up with a Q1 Vs of either V2-Vt or whatever Q1 Vg-Vt is with Q2 on, then performance will be poor since Vt varies with temperature and from unit to unit, and Q1 can have large Vds when Q2 is on.

The problem is that Q1 Vg is not referenced to Q1 Vs, so Q1 can't be turned fully on until Vs is constrained by conduction through its channel and can't be turned fully off until Vs is constrained by ground.

A drive that uses a charge pump (or something like that) and is referenced to the source of Q1 will be needed for proper gate control.

  • \$\begingroup\$ It's expected that there's a voltage at V2 and V1. V2 is expected to be at least at V1+Vt+V_(whatever extra slack you want for temperature variation). Choosing the correct resistors will allow Vg on Q1 to be brought down to ~V1 when Q2 conducts. I don't follow what the issue is. \$\endgroup\$ – horta Jun 6 '14 at 23:54
  • \$\begingroup\$ @horta That is a good example of the issue. If Vg drops to ~V1 when Q2 is on then Vs will be V1-Vt, not off. \$\endgroup\$ – gsills Jun 7 '14 at 20:55
  • \$\begingroup\$ Ah I understand where you're coming from. I should have noted that the output voltage was assumed to be between two known voltages and would not drop below Vg. I'm starting to think that my question was terribly worded. Sorry about that. \$\endgroup\$ – horta Jun 9 '14 at 14:01

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