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I understand that gate count is not a measure for FPGA designs as it is in ASIC world. However, I have to compare the structural efficiency of two designs, one in FPGA and the other one in ASIC, by comparing their equivalent circuit area or gate count. For ASIC it is straightforward to obtain the gate count, however for FPGA, is there any approximation by which I can get the equivalent gate count for a design with the following specs?

FPGA: Xilinx XC3S1200E-4FG320

MULTs: 3(18x18) FFs:511 LUTs:611 Slices:521 Taps/bits: 10/16

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  • \$\begingroup\$ Do a bit of research to work out how many gates would be required to implement each of those primitives? \$\endgroup\$ – markt Jun 10 '14 at 9:44
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There really isn't one answer as there is so many different ways to instantiate a synthesizable design.

One way would be to use your synthesizable RTL and resynthesize it with another tool and target a different library.

For hand counting, you just need to look at your Mults, FFs and LUTs. The slices are organization hierarchical blocks and taps are routing resources, neither should affect you gate count majority.

Mults and FFs are easy enough to account, for the main issue is going to be your LUTs as there is often way more capability embedded into a LUT than is used, or the LUTs are cascaded in a particular fashion to prevent a speed impact. It will be more accurate to look at the logic cloud in your RTL map to the equivalent 2 input gate.

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Well, this is a common question for everyone who is used to design for ASIC, but as you mentioned yourself, it is hard to get a correct estimate of the gate count from the report of the FPGA tools.

You can make a guess by getting this from your report:

  • Number of flip-flops or registers
  • Number of logic blocks used for logic
  • Memory blocks or other special functions used in your design

The report also shows the number of LCs used for routing, those are not interesting for your gate count, but if you use those numbers, you will be able to calculate a rough estimate of the number of gates in your design, but the accuracy is not going to be very good.

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