I understand that gate count is not a measure for FPGA designs as it is in ASIC world. However, I have to compare the structural efficiency of two designs, one in FPGA and the other one in ASIC, by comparing their equivalent circuit area or gate count. For ASIC it is straightforward to obtain the gate count, however for FPGA, is there any approximation by which I can get the equivalent gate count for a design with the following specs?
FPGA: Xilinx XC3S1200E-4FG320
MULTs: 3(18x18) FFs:511 LUTs:611 Slices:521 Taps/bits: 10/16