I'm having trouble figuring out how the longest stage of a pipeline is calculated given the following:

"Your processor has a 3-stage pipeline where the delay is 26ns through the first stage, 40ns through the second stage, and 26ns through the third stage. The propagation delay for latches is 4ns. What is the speedup, over an infinite number of instructions, of the given pipeline over an unpipelined version assuming the logic is the same for both versions?"

Is the pipeline cycle time equal to the longest stage plus two latch propagation delays or just one? I understand that there will be a latch delay before and after entering the longest stage, but I'm not sure whether to count both of the delays or just one when calculating the pipeline cycle time.

  • 1
    \$\begingroup\$ Insufficient data. The pipeline cycle time includes the propagation delay of the latches, the largest combinatorial logic delay, and the input setup time of the next latch. Since a value for the last item is missing, the question can't be answered. \$\endgroup\$
    – Dave Tweed
    Jun 9, 2014 at 22:06
  • \$\begingroup\$ Model the overall delay through a variable number of stages and it should be clear that you go through only one latch per clock cycle (at least if your pipeline is functioning as a pipeline). Depending on nature of your inputs though, you may need to have a latch at the input forming a sort of 0-th pipeline stage. \$\endgroup\$ Jun 9, 2014 at 22:32
  • \$\begingroup\$ Is this about electronic design? If this was was water pipes and valves, and the times were in tenths of a second, how would the answer differ? \$\endgroup\$
    – Kaz
    Jun 9, 2014 at 23:04

1 Answer 1


Before pipelining, total delay = 26 + 40 + 26 = 92ns/instruction.

If an input is fed at 0ns, then 1st stage output will be obtained at 26ns, 2nd stage output at 70ns and final output at 100ns. So the maximum delay is 44ns (= 70-26, in the 2nd stage). So for pipelining, time period of clock must be at least 44ns.

Since infinite number of instructions are executed, the initial latency can be neglected. Then after pipelining, time taken for executing one instruction will be one clock period.

After pipelining, total delay = 44ns/instruction.

  • \$\begingroup\$ Wouldn't it take longer than 128ns to execute three instructions? Don't the 2nd and 3rd instructions in the pipe add more time since they can't use the same hardware simultaneously? \$\endgroup\$ Jun 11, 2014 at 23:04
  • \$\begingroup\$ Yes. It will take 132ns to execute three instructions. Please see edited the answer. \$\endgroup\$
    – nidhin
    Jun 12, 2014 at 3:58
  • \$\begingroup\$ Ah, I see. Thanks. That makes the whole thing clear. \$\endgroup\$ Jun 12, 2014 at 21:24

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