I'm having trouble figuring out how the longest stage of a pipeline is calculated given the following:
"Your processor has a 3-stage pipeline where the delay is 26ns through the first stage, 40ns through the second stage, and 26ns through the third stage. The propagation delay for latches is 4ns. What is the speedup, over an infinite number of instructions, of the given pipeline over an unpipelined version assuming the logic is the same for both versions?"
Is the pipeline cycle time equal to the longest stage plus two latch propagation delays or just one? I understand that there will be a latch delay before and after entering the longest stage, but I'm not sure whether to count both of the delays or just one when calculating the pipeline cycle time.