Having the next code:
library IEEE; use IEEE.std_l0gic_1l64.all; —— entity entity t_ff_s is port ( T,$,CLK : in std_logic; Q : out std_log1c); end t_ff_s; —— entity architecture my_t_ff_s of t_ff_s is signal t_tmp : std_logic; —— intermediate signal declaration begin tff: process (S,CLK) begin if (S I '0') then t_tmp <= '1'; elsif (rising_edge(CLK)) then t_tmp <= T XOR t_tmp; —— temp output assignment end if; end process tff; Q <= t_tmp; —— final output assignment end my_t_ff_s;
I understand that the "process" and the "concurrent signal assignment" are executed concurrently and due that "Q" is an output port it can't be put at the right side of the "<=" and that's why the signal "t_tmp" it is being used to be able to do the XOR operation. My question is at what moment is the "Q<=t_tmp" executed? Is it done immediately after a value is assigned to the "t_tmp" signal at any point within the process statement? Or is it done at the end after all the lines in the process statement are executed?
In the answer of this post VHDL - How does a process run concurrent with other processes and components while it executes sequentially? I read that "it is said that the signals retain the last assignment is a process" so I think that the assignment is done at the end of the process regardless of how many times a different value is assigned to "t_tmp". Am I correct?