# When is the concurrent signal assignment executed?

Having the next code:

library IEEE;
use IEEE.std_l0gic_1l64.all;
—— entity
entity t_ff_s is
port ( T,\$,CLK : in std_logic;
Q       : out std_log1c);
end t_ff_s;
—— entity

architecture my_t_ff_s of t_ff_s is
signal t_tmp : std_logic;   —— intermediate signal declaration

begin
tff: process (S,CLK)

begin
if (S I '0') then
t_tmp <= '1';
elsif (rising_edge(CLK)) then
t_tmp <= T XOR t_tmp;   —— temp output assignment
end if;
end process tff;

Q <= t_tmp;                   —— final output assignment
end my_t_ff_s;

I understand that the "process" and the "concurrent signal assignment" are executed concurrently and due that "Q" is an output port it can't be put at the right side of the "<=" and that's why the signal "t_tmp" it is being used to be able to do the XOR operation. My question is at what moment is the "Q<=t_tmp" executed? Is it done immediately after a value is assigned to the "t_tmp" signal at any point within the process statement? Or is it done at the end after all the lines in the process statement are executed?

In the answer of this post VHDL - How does a process run concurrent with other processes and components while it executes sequentially? I read that "it is said that the signals retain the last assignment is a process" so I think that the assignment is done at the end of the process regardless of how many times a different value is assigned to "t_tmp". Am I correct?

When looking to understand what's happening in a HDL in general, it's a good idea to think about what's going on in the actual hardware. There isn't a concept of "execution" in an FPGA in the same way that there is in a CPU. I was taught that when you read a concurrent statement, you read it as Q is driven by not out1.

In hardware, the above concurrent statement (Q <= not out1), is the equivalent of this:

simulate this circuit – Schematic created using CircuitLab

When does the output change? After the input changes + some delay that's a characteristic of the chip. Is this called execution? No.

Processes are constructed using flip flops which are clocked. For example, this:

p1:process(clk)
begin
if rising_edge(clk) then
b <= a
c <= b
end if;
end process;

produces

simulate this circuit

Since the flip flop is clocked, the driven outputs only change on the clock edge, even though the input may have changed sometime before. Could this be called execution? No.

Writing HDL really needs a change of mindset away from the CPU to a place where you actually consider the hardware implications of what you're coding. You're describing the hardware.

As an exercise, take a look at the final block diagram for the code that you write once it's been built and see if you can identify where the concurrent statements are and where the processors are. it's quite interesting to see.

Disclaimer: I've simplified what's going on in the FPGA quite a bit. It doesn't use discrete gates and I don't think it uses D-type flip flops either, so there are some inaccuracies here, I picked those components for illustration purposes.

• man, that circuit simulator is a user-bait site. They tell you to create an account in order to save your circuit and export it. You create the account, and then they tell you you need to buy a license to do the same. Shame on them, I'm disappointed. – Johannes Schaub - litb Aug 13 '17 at 18:15
• @JohannesSchaub it never used to be like that. A couple of years ago it was a really nice site and (I believe) EE stackexchange worked with them to get it properly integrated so we could use circuits nicely in answers. I'm sorry to hear it has changed. – stanri Aug 14 '17 at 6:07

Concurrent statements are executed whenever there is a change in value of signals on the right hand side of the statement.

Your statement Q<=t_temp will get executed whenever there happens a change in value of t_temp and the action happens immediately after the signal assignment.

$% By this statement, *"it is said that the signals retain the last assignment in a process"*, I think he meant to say that the stable value of a signal after executing a process is the last value assigned to it in the process.$

For example, if the assignment is done at the end of the process, then the following code will always produce output Q <= 0 and I don't think so.

p1:process(clk)
begin
if clk = '1' then
count <= Count-1;
end process;

p2:process(trigger)
begin
if trigger = '1' then
out1 <= '0'
wait until count = 0;
end if;
out1 <= '1'
end process;

Q <= not out1;