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Do I need to clear the pending status of an interrupt in the interrupt service routine of an ARM Cortex-M0 MCU?

Could not find information on this on the web.

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  • \$\begingroup\$ I can't answer for this specific processor, but in general, yes, you need to clear the pending interrupt in the ISR. If you don't, the interrupt will remain asserted and as soon as you exit from the ISR, it will be triggered again. \$\endgroup\$
    – DoxyLover
    Jun 11, 2014 at 17:22

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No, you don't need to clear the pending status in the NVIC, that is done automatically when the interrupt is serviced (see Joseph Yiu, The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors, 3rd Edition, page 247).

However, you may need to clear the condition causing the interrupt on the specific peripheral.

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  • \$\begingroup\$ "you may need to clear the condition causing the interrupt on the specific peripheral" - could you please explain this sentence a little bit more? When I need to do that? Which peripherals? \$\endgroup\$
    – RHaguiuda
    Jun 13, 2014 at 11:50
  • \$\begingroup\$ Some peripherals set a flag for the interrupt that needs to be reset in the interrupt routine. For example, the SCT on LPC8xx has the EVFLAG register, where an event can cause an interrupt by setting its corresponding bit. If it is not cleared the interrupt will be triggered again immediately. \$\endgroup\$
    – starblue
    Jun 14, 2014 at 7:23
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    \$\begingroup\$ I find incredible that such important information is not in the user manual of the part. You have actually buy a book to find it out! This is one of the greatest challenges in my opinion when learning ARM programming. The information you need is spread in manuals, datasheets, books, websites, code examples and you have the job to mine it from places that you can even imagine! \$\endgroup\$
    – RHaguiuda
    Jun 25, 2014 at 11:36
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    \$\begingroup\$ Actually it should be in one of the ARM documents, but I couldn't find it there. I think it is an oversight, as the ARM ARM DDI0403 is very detailed otherwise (lots of pseudocode). It should be done in SCS_UpdateStatusRegs(), which unfortunately is not provided. \$\endgroup\$
    – starblue
    Jun 25, 2014 at 16:25
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IN PIO one has just to read the PIO_ISR status inside of interrupt procedure. In other case it makes the interrut pending directly after interrupt exit. I'm currently not sure, but i thing Atmel ASF handler is doing it automatically, but going into lower level, one has not to forget to do it self.

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Thanks abc for the hint. It took me weeks to find that out, since ASF handler is NOT doing it automatically. Since I only have one pin active for interrupt, I do not need to read that register for pin locating. Now, always reading that register everything’s working fine.

Hint: In the PIO user interface of the SAM E70 (my processor) data sheet under the PIO_ISR register description, is the following sentence: „1: At least one input change has been detected on the I/O line since PIO_ISR was last read or since reset.“ I think that’s really hard to find.

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