This has been bothering me for some time. Why is it that the overdrive voltage of the bottom transistor in a cascode controls the DC current, and not the Vgs of the top transistor? Similarly, in an NMOS diff pair with a current mirror on the bottom, why does the overdrive voltage of the mirror control the current, and not the common-mode voltage of the pair?

This came to mind when I read in a textbook that it is improper to draw a current source feeding the drain of a transistor, rather than pulling current from the source.


2 Answers 2


Referencing the diagram from the linked article:

enter image description here

The drain current of either transistor is mostly determined by the respective gate-source voltage.

For the lower transistor, the gate-source voltage is just the input voltage

$$v_{GS1} = v_{IN}$$

For the upper transistor thought, the gate-source voltage is

$$v_{GS2} = 0 - v_{D1}$$

where, in this example \$v_{D1} < 0 \$.

Now, the drain voltage of the lower transistor \$v_{D1}\$ will, essentially, be whatever it needs to be such that the upper transistor transistor current matches the lower transistor current.

For example, if the input voltage rises, the drain current of the lower transistor will increase which will act to reduce \$v_{D1}\$ (make \$v_{D1}\$ more negative) which increases \$v_{GS2}\$ thus increasing the drain current of the upper transistor.


The current in a series-connected circuit is determined by whichever device passes the lowest amount.

In a cascode circuit, the upper transistor's base/gate is held at a fixed voltage, which means that it will pass essentially arbitrary amounts of current with small changes in its emitter/source voltage. It will always be able to pass more current than the lower transistor, so it's the lower transistor that rules.

It's the same thing with the differential pair; raising the common-mode input voltage would allow more current to flow, so the current source becomes the limiting device, and so the voltage at the node where they're all connected simply rises to track the common-mode input voltage.

I'm not sure how your last statement is related; using a current source as a drain load is actually quite common in circuits that require high voltage gain.


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