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Is it possible to run code on the ARM Cortex M architecture from locations other than the onboard flash memory (such as another flash chip, SD card)?

If so, how?

If not, what microcontroller architecture does permit this?

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  • \$\begingroup\$ I know at least some cortex M chips can run code from RAM, and you can copy the code from SD to ram if you have enough. ARMs are pretty nice though I don't know much about them but I'm sure someone has a more direct way. \$\endgroup\$ – EternityForest Jun 12 '14 at 11:50
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    \$\begingroup\$ AFAIK all Cortex chips can run code from internal RAM. \$\endgroup\$ – Wouter van Ooijen Jun 12 '14 at 11:59
  • \$\begingroup\$ Yes, but many of them are slower at that than they are when executing from flash, given a quasi-harvard architectural optimization which assumes flash is primarily for code and RAM primarily for data. \$\endgroup\$ – Chris Stratton Jun 12 '14 at 14:03
  • \$\begingroup\$ True Chris, but IME only when there is data/code contention. In some cases running from RAM is even faster. \$\endgroup\$ – Wouter van Ooijen Jun 12 '14 at 15:29
  • \$\begingroup\$ @Chris Stratton In my experience with NXP controllers internal RAM is much faster than flash (no wait state compared to 9 at 200 MHz, giving a factor of three with prefetching/caching by the flash acceleration unit). \$\endgroup\$ – starblue Jun 14 '14 at 8:07
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ARM Cortex M allows code execution from Flash, internal and external RAM. External RAM (if available) needs to be set up before it can be used.

You may need to change the linker script and/or startup code, but that depends on the compiler you use.

The CCC r0ket for example loads external code into RAM and executes it.

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  • \$\begingroup\$ That's good to know, but do you need to wire the RAM chip to a specific pin, or does it work with any SPI pin? \$\endgroup\$ – manuel.rivera Jun 12 '14 at 12:50
  • \$\begingroup\$ Depends on the actual µC that you use. There are many variants. \$\endgroup\$ – Turbo J Jun 12 '14 at 13:16
  • \$\begingroup\$ I'm using the ARM Cortex M4. \$\endgroup\$ – manuel.rivera Jun 12 '14 at 13:17
  • \$\begingroup\$ No, execution from SPI memory is unlikely to be supported. But there might in some cases be a bootloader which will read the contents of an SPI memory into RAM and execute it there. \$\endgroup\$ – Chris Stratton Jun 12 '14 at 14:02
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    \$\begingroup\$ Have a look at the link I posted. The CCC r0ket loads a small program (l0dable) from external SPI flash into a 2,5 KB RAM window and executes it. Schematic and full source included. \$\endgroup\$ – Turbo J Jun 12 '14 at 14:20
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The Cortex-M architecture doesn't put any restriction on the memories, it depends on the memory interfaces that are available on a specific controller.

For example, the LPC43xx allows to execute code from internal flash and RAM, external static RAM, NOR flash and serial flash (SPIFI). I'm not sure about code execution in dynamic RAM as it is in an address range not normally used for code, but probably it is possible, too.

Note that external memories will generally be slower than internal ones. The fastest is internal RAM.

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    \$\begingroup\$ Execution from serial flash is likely to become more popular since it is much cheaper than integration on SoC, and bandwidth is quickly increasing. Add a bit of cache and off you go (I've evaluated a SoC with this tech already, no public info available) \$\endgroup\$ – Adriaan Jan 29 '15 at 18:53
  • \$\begingroup\$ @Adriaan Yes, a flashless LPC43x0 and SPIFI flash is a nice design. You can have much bigger code, and by putting time-critical code in internal RAM you get the speed, too. If you want to play with it, take a look at LPC-Link2 from EmbeddedArtists (get two, one as a debug interface and one as the target). \$\endgroup\$ – starblue Jan 31 '15 at 16:32
  • \$\begingroup\$ different one. I've played with an IoT SoC. Strength of cached execute-in-place is the additional space at some performance. Disadvantage is that it costs a lot of time to optimize for this tradeoff. It loses some of the nice simplicity of the Cortex M3/M4 is gone... \$\endgroup\$ – Adriaan Feb 2 '15 at 6:30

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