On an ARM cortex m0+:

How many cycles does it take to perform multiplication of single precision floats and store them into a float? i.e. x = a*b; Where x, a, and b are single precision IEEE 754 float point... and what if they were both double precision?

Bonus Question: How many cycles does it take to shift an integer by 16 bits and store it into another integer. i.e. x = (y>>16); Where x and y are 32-bit signed integers.


Compiler I will be using is the ARM gcc compiler

The reason I ask this question, is I plan on using q31, but I wanted to see what the difference really would be

  • \$\begingroup\$ The ARM Thumb2 instruction set is so efficient (barrel shifter allows any number of shifts in one cycle simultaneous with any other instruction) that there is a surprisingly small difference between soft and hard float, for example when compared to an M4. Hardware multiply accumulate (MAC like single*single --> +=double) for DSP is where you really start to see a difference. Just search multiply speed for M0 versus M4. \$\endgroup\$ Jun 14, 2014 at 5:59
  • 1
    \$\begingroup\$ What do you want to do? If you need performance on the Cortex-M0 you should probably simulate fixed point computations with integers. \$\endgroup\$
    – starblue
    Jun 14, 2014 at 7:45
  • \$\begingroup\$ yea, i will be using q31 format... but wanted to compare with float \$\endgroup\$
    – hassan789
    Jun 14, 2014 at 14:32
  • 2
    \$\begingroup\$ The Cortex-M0 doesn't support the full Thumb2 instruction set. It does not allow shifting simultaneous with other operations and, more significantly, it does not include any instruction to compute the upper 32 bits of a 32x32 multiply. \$\endgroup\$
    – supercat
    Sep 10, 2014 at 17:08

1 Answer 1


1 and 2: there's no hardware floating point unit on the M0, so it depends on your compiler alone. Expect on the order of tens to possibly low hundreds of cycles for single precision, with full IEEE compatibility. As for double precision, you're probably looking at high hundreds, maybe even breaking the thousand-cycle barrier, again assuming full IEEE compatibility.

3: single cycle.

  • \$\begingroup\$ Note that a 32 bit integer multiplication may take either 1 or 32 cycles, depending on the hardware. IMHO it is likely that it is used in the floating-point multiplication, so this may have some effect on the execution time. \$\endgroup\$
    – starblue
    Jun 14, 2014 at 7:42
  • \$\begingroup\$ How about with gcc... also, I thought the ARM cores were hardware independent? \$\endgroup\$
    – hassan789
    Jun 14, 2014 at 14:35
  • \$\begingroup\$ @starblue: I think Cortex m0 specifies a single-cycle 32x32 multiply to 32-bit result, but does not allow any way to compute a 32x32->64 multiply except by decomposing the original value into smaller pieces. \$\endgroup\$
    – supercat
    Sep 10, 2014 at 17:10
  • \$\begingroup\$ @hassan789 The single cycle multiplication is an optional feature. Of NXPs controllers the standalone M0s tend to have it, while the M0s on the LPC43xx multicore controllers don't. \$\endgroup\$
    – starblue
    Sep 11, 2014 at 10:56
  • \$\begingroup\$ @supercat Yes, that's true. It should still help performance if you use it to do 16x16 to 32 bits. \$\endgroup\$
    – starblue
    Sep 11, 2014 at 10:59

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