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I know the ideal integrator topology and output equation. But - what is the affect of connecting a supply at the positive input (instead of GND)? How can that be calculated mathematically for NODE1 and NODE2?

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ Initial condition can be found (assuming VC3 = 0), and equate the two inputs for the op-amp not saturated to get the current through C3. \$\endgroup\$ Jun 16, 2014 at 14:47
  • \$\begingroup\$ P.S. Without looking up the datasheet for the OP97, I'm pretty sure it's not going to work very well with a +1V supply and a +1V input. Also, the bottom one should presumably be negative. The way you've drawn it, the chip doesn't have any supply voltage. \$\endgroup\$ Jun 16, 2014 at 15:02
  • \$\begingroup\$ The supplies are +/- 15V and the +IN is +5V. I just updated it. \$\endgroup\$ Jun 16, 2014 at 15:57
  • \$\begingroup\$ Better, but the bottom 15V supply should be flipped. It still has no supply voltage. \$\endgroup\$ Jun 16, 2014 at 16:01

2 Answers 2

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Following the superposition theorem you can calculate Vout (node 2) as a result of Vn1 (node 1) and V1=1V:

Vout=V1 + (V1-Vn1)/s*R1C3

For V1=0 this simplifies to the well-known MILLER integrator formula Vout=-Vn1/S*R1C3.

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  • \$\begingroup\$ What is the s? \$\endgroup\$ Jun 16, 2014 at 15:59
  • \$\begingroup\$ It is common practice to use for "jw" the symbol"s". \$\endgroup\$
    – LvW
    Jun 16, 2014 at 20:08
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The result would be a ramp on the output, which will eventually saturate at the plus or minus rail, depending on the sign of the difference between V1 and node 1. As for node equations, all the current through R1 goes right into C3, charging it, with no means of discharging it. Since $$ i= - C \frac{dV}{dt} $$ Then $$ V=\frac{-1}{C}\int i \: dt $$

i would just be (Vnode1 - V1)/R1

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  • \$\begingroup\$ I just wanted to look at that piece of circuit first. Both nodes are connected to other parts in a larger circuit \$\endgroup\$ Jun 16, 2014 at 15:59

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