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I've recently purchased the PMOD AMP1 module from digilent for use with my Nexys 2.

When I program the demo project and plug headphones or speakers on the headphone output I can hear a barely audible, extremely high pitch tone on the headphone out.

After reading through the source I realised this project is setup for a 100Mhz clock while my board's clock is 50Mhz. I modified the synth.vhd as below:

entity synth is
    port(clk : in std_logic;
          syn_out : inout std_logic_vector(7 downto 0));
end synth;

architecture Behavioral of synth is

signal sclk : std_logic_vector(10 downto 0);

begin
    process(clk)
        begin 
            if clk'event and clk = '1' then
            -- divide a clock by "10111010101" (1493) which is about the value of 100M/256/261.6
            -- where 100M is the clock frequency on a Nexys3
            -- 256 is the number of points in the sine wave table
            -- 261.6 is the frequency of a middle C
                if sclk = "1011101010" then -- MODIFIED decreased by half for 50Mhz clk (746 is new clock divider)
                    --"11111111" is 255 is the maximum point in the sine wave table
                    if syn_out < "11111111" then 
                        syn_out <= syn_out + 1;
                    else
                        syn_out <= "00000000";
                    end if;
                    sclk <= "00000000000";
                else
                    sclk <= sclk + 1;
                end if;
            end if;
    end process;

end Behavioral;

As per nidhin I need to modify the pwm file as well:

constant ckPwmRange: integer:= 5;
   -- LSB in the cntPwm alias of cntDiv
signal cntPwm: std_logic_vector(ckPwmRange+8 downto 0);
   -- the most significant 8 bits are used for PW Modulator:
   -- cntPwm counts 100MHz/2^ckPwmRange

I think that since the clock is running half as fast, the cntPwm should also be halved. I think this means ckPwmRange should be 2.5 but instead could I replace the cntPw assignment as:

signal cntPwm: std_logic_vector(ckPwmRange+7 downto 0);

?

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  • 1
    \$\begingroup\$ Have you tried changing the pwm.vhd file? because it also assumes clk = 100MHz. \$\endgroup\$ – nidhin Jun 17 '14 at 9:08
  • \$\begingroup\$ edited my question, you're right Im just trying to work out how to scale down the counter in pwm.vhd now \$\endgroup\$ – ioseph Jun 17 '14 at 12:36
  • 1
    \$\begingroup\$ why don't you try both the methods and see what happens? \$\endgroup\$ – nidhin Jun 17 '14 at 12:55

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