# Generate State Diagram from VHDL Code?

Is there a tool which generates State Diagrams from VHDL code? Also is there an easy way to indent VHDL code like in Visual Studio if I press ctrl + i it indents.

• emacs has a "beautify VHDL" mode which is absolutely great. <CTRL-C> <CTRL-B> key combo. Jun 18 '14 at 8:03
• if you use Quartus and your code is written in a state machine template you go to RTL viewer, state machine. Jun 18 '14 at 9:01