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If we have a circuit in dynamic logic:

image

What should the size of the charge transistors (Qe and Qp) be? I know that increasing the size improves the speed but also increases the dissipation, and that it doesn't affect the functionality.

If the highest transistor width of my pull-down-network (PDN) is \$N\cdot\lambda\$, should my size for charge transistor be something like: \$f(N)\cdot \lambda\$ ?

Thanx!


P.S. Image reference: Sedra, Smith - Microelectronic Circuits

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  • \$\begingroup\$ What's in your pull down network? Really, what you should care about in that is the smallest transistor width inside that because that's what's going to limit your charge/discharge time. \$\endgroup\$ – horta Jun 21 '14 at 22:55
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In normal static CMOS logic, you need to maintain equal rise & fall times because there is both PDN & PUN networks. But in this footed Dynamic logic, you have only PDN network. So during precharge period (\$\Phi=0\$), PDN network is idle and charging through PMOS can occur more slowly than static CMOS logic. Therefore, PMOS transistor can have small width.

For example, consider this 2-input NAND:

enter image description here

Here, PMOS transistor is chosen to have unit width (W) and thus it has twice the unit resitance (2R), assuming \$\mu_n=2\mu_p\$. But for NMOS transistors we need to have unit resistance (R). Since there are three series NOMS transistors, each will have three times the width of unit transistors(3W). So the total resistance is equal to unit resistance (R).

As you can see, PMOS has the twice the resistance than the total NMOS transistors' equivalent resistance. So the rising delay will be larger than the falling delay. But it wont affect the performance, since during precharge, inputs are idle.

You can follow the same technique for other PDN networks. This example was taken form "CMOS VLSI Design - Weste & Harris'

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For CMOS logic, you may want to look for the topic of "logical effort." This describes, in detail, some formulas to compute the sizing off pmos vs nmos to balance out rise and fall times.

A rule of thumb is Lp = 2 * Ln, where Lp is the pmos gate length and Ln is the nmos gate length. You should be able to characterize this in your simulation software.

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  • \$\begingroup\$ Since the mobility of holes is ~ 1/2.3 that of electrons why are you proposing that the PMOS transistor be further weaken by increasing it's length?\$ G_m = K \mu \frac{w}{l}\$ normally you'd increase it's width by a factor of 2.3 to compensate. \$\endgroup\$ – placeholder Jun 22 '14 at 4:59

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