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My project is finished and Xilinx gives lots of statistics in the summary like :

enter image description here

enter image description here

How shall I evaluate these values, what can I say about them? What means what? Is this report good or bad? With what can I compare my results with?

Also timing constraints failed with below stats:

enter image description here

Is there a way I can fix this and what can I say about it? What would be the source of the problem? I would be glad if you can give me a hand!

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In general: If your design does not meet timing, this is bad. You might see errors on the FPGA that you will not understand. So always get rid of such warnings before you start evaluating on real hardware.

The timing constraint that has not been met indicates that you have a 100 MHz clock. Is this the case? What is your target FPGA? What kind of design entry method do you use (Schematic or HDL)?

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  • \$\begingroup\$ Hi Simon, thanks for your attention, this was a school project and already finished... However the target device you can see on the screenshot. \$\endgroup\$ – Anarkie Sep 15 '14 at 13:06

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