# Fixing 1 failing timing constraint in Xilinx

In the end of my project I have a timing constraint failure as follows :

clk_in is the 100 Mhz system clock on ML507 I don't know why it is not meeting the criteria, I don't know what the criteria is as well, how can I fix this, any idea what can cause this failure? Although the project is working. How can I debug this?

• You need to look at the detailed timing report, which will tell you exactly which path(s) are failing. Jun 24, 2014 at 10:05
• you clock period is 10ns, whereas maximum datapath delay is 11.902ns. Either you need to reduce the datapath delay or decrease clock frequency. There are many techniques for fixing setup violation in ASIC, I'm not sure which ones are applicable for FPGA. eg electronics.stackexchange.com/questions/73456/… Jun 24, 2014 at 10:17
• @DaveTweed Is this detailed timing report at the end of the Sythesis run? Where can I find it? Also about this question electronics.stackexchange.com/questions/116372/… can you make a comment at least? Jun 24, 2014 at 10:21
• From your previous question there were 398 violations of the same timing constraint. What did you do to reduce the number to 262?
– user8352
Jun 24, 2014 at 12:22
• From Virtex-5 FPGA User Guide - "The DCM contains a delay-locked loop (DLL) to completely eliminate clock distribution delays, by deskewing the DCM's output clocks with respect to the input clock."
– user8352
Jun 24, 2014 at 13:06