What does limp mode mean in this sentence below?
Make sure the PLL is not running in limp mode.
Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.Sign up to join this community
In this case a PLL in "Limp Mode" would suggest it's still outputting a signal as best it can, however it won't be phase locked like it should
Limp Mode or Limp Along Mode is often a feature used to make sure something will keep running even in the event of certain failures... often seen in cars and planes..
Quoting from the wiki
Automotive tests itself to enhance safety and reliability. For example, most vehicles with antilock brakes test them once per safety interval. If the antilock brake system has a broken wire or other fault, the brake system reverts to operating as a normal brake system. Most automotive engine controllers incorporate a "limp mode" for each sensor, so that the engine will continue to operate if the sensor or its wiring fails
Critical flight equipment is normally duplicated, or redundant. Less critical flight equipment, such as entertainment systems, might have a "limp mode" that provides some functions.
The quoted sentence sounds it's referring to the "limp mode" which is implemented in some microcontroller's PLL circuitry. If the reference clock fails by either stopping altogether or running at a speed which is nowhere near correct, the PLL will switch to a "limp mode" in which it ignores the reference clock and instead operates at a speed which is guaranteed to be no faster than the requested speed, but is likely to be much slower (e.g. a part might normally be expected to output a 16MHz clock, but limp mode might run at a rate of 10MHz +/- 5 Mhz). Even if combinations of temprature, voltage, and other factors would cause the limp-mode oscillator to run faster than expected, it would still stay below the 16Mhz specified speed.
The normal assumption regarding limp mode is that small-scale timings are apt to be dominated more by minimum-time requirements than maximum-time requirements. For example, a memory chip might require that the controller wait 60ns after clocking out each byte before clocking out the next one; such a requirement would be met if the controller was running at 16MHz (clocking one bit every 62ns), or if it was running slower, but would not be met if it was running 16.67Mhz or faster). The controller might not be fast enough to perform its normal duties, but the absence of a properly-regulated clock would be taken as a signal that the controller should switch to a mode that doesn't require it to do so much. For example, an automatic-guided vehicle might need a 10KHz feedback loop running at a known rate to operate at full speed, but might be able to operate at somewhere around 1/10 normal speed using a feedback loop which is known to be running at something between 2KHz and 6Khz. Such operation might not be fast enough for the machine to perform its normal functions, but may allow the machine to pilot itself to some out-of-the-way location where it could await servicing.