Suggestions for Ternary Computer Parts

Question

I am thinking of creating a ternary computer from scratch, mostly as a hobby project, are there any parts out there that I could use? Or would I have to create them from scratch? If so, what would be a good method?

I was thinking of a balanced Ternary system, much like Nikolay Brusentsov's Setun. I am familiar with VHDL and I am quite familiar with Binary logic. I was hoping to avoid using digital components, such as FPGAs and make a purely ternary computer, so I was thinking more of what to use a logic units, in lieu of transistors.

Answer 1

A PMOS over a NMOS would work as a ternary inverter if the supply voltage is low (slightly above the threshold voltage):

^{simulate this circuit – Schematic created using CircuitLab}

At -0.5V input, the output will be raised by M2 to 0.5V.
At 0V input, both transistors will be "Off" and the resistors will pull the output back to 0V.
At 0.5V input, M2 will shut off and M1 will turn on pulling output to -0.5V.

A Ternary NOR could be this:

^{simulate this circuit}

Truth Table:

00 0
0+ -
0- +
+- 0
++ -
-- +

A Ternary NAND could be this:

^{simulate this circuit}

Truth Table:

00 0
0+ 0
0- 0
+- 0
-- +
++ -

I would assume more complicated ternary gates could be made based on similar principles.

It's interesting to note that a major disadvantage of this topology is the loss of speed due to RC settling times where the C is inherent capacitance of the transistors. One possible advantage of this may be the required low-voltage and therefore low power draw of the circuits.

Answer 2

You're not going to find any logic ready-made. However, you can build up your own logic using an FPGA. I'd try mapping 2 binary bits to a single ternary bit by mapping 11 to 1, 10 or 01 to unknown, and 00 to 0. Then you would define your ternary logic operations on sets of these two bits. Likewise, for instance, you could then use existing memory at half data width, that is an 8-bit-wide RAM would be used as a 4-bit-wide ternary RAM, etc. You'll need to become proficient with VHDL for the design process, or if you like you can get a schematic entry option for FPGA design.

Answer 3

I'm dredging up a really old post here, but my answer was voltage comparators (not binary comparators). My project thus far is documented at https://hackaday.io/project/6284-tern-physical-implementations-of-ternary-logic

Answer 4

Recently I realized a prototype of Ternary Balanced Electronic Calculator (TBEC) based on three locgic levels -1, 0, 1 (trit). It consists of an 8 trit ternary memory made with ternary Flip-Flop D-latch, 3 ternary Full-Adder and one ternary Half-Adder, and finally by a ternary decoder which allows you to view the addenda of the operation (4 trit + 4 trit) and the result (5 trit) on LEDs. The management of the keyboard (1 ternary digit), the enabling of the memory and the decoder is managed through a PIC microcontroller. the device is schematized in the following figure:

I later improved the project interfacing the TBEC with a common PC. As previously said, each addendendum is made up of 4 trit, so the Calculator can process numbers ranging from -1-1-1-1 to 1111 (-40 to 40 decimal places) and give a result from -10001 to 1000-1 (-80 to 80 decimal places). From now on for convenience we will denote -1 as 2.

For this reason, the PC transmits to the TBEC unit for each addend two numbers, the first of which constitutes the quantity of quarantines into which the addend is decomposed and the second the remainder of the difference between the value of the addend and the quantity of quarantines in which the latter is decomposed

ADD1 = n40 * 40 + R1
ADD2 = n40 * 40 + R2
Where R 1= ADD1 – n40 * 40
R 2= ADD2 – n40 * 40

Once received the four numbers constituting the addenda, the ternary unit performs the sum respectively of the quantities of quarantines and the remainders and returns it to the PC. For example, if you want to add 85 + 41, 0012, 0122 will be transmitted to be added to 0001, 0001, obtaining 00010, 00120 in reception.

The memory made up of eight ternary flip-flops D latch stores the two addenda to be presented to the adder.

As we said at the beginning, the PC communicates with the TBEC unit through a UART serial protocol, whereby the information travels in byte packets. Hence the need to encode the ternary number from 2222 to 1111 through the eight bits of each single packet, therefore two bits are required for each trit as follows: 0 <=> 00, 1 <=> 01, 2 <= > 10

In the above example 0012 is encoded in one byte as 00.00.01.10. 0122 is encoded in one byte as 00.01.10.10

The result at the adder output is on five trit so it needs a coding on two bytes: 00010 is transmitted as 00.00.00.00 00.00.00.10 00122 is transmitted as 00.00.00.00 00.01.10.10

YOUTUBE VIDEO https://youtu.be/PmED4PfKZgc