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I got to know 4 circuits used for Precharging in SRAM. I have few questions regarding circuits explanation:

Precharge and Equalize Circuit

Diagram (a):

Q1: It mentions it as diode-connected NMOS pair. Why?

Q2: This burns more power during write operations where one of the bitlines is pulled low by the write amp, again fighting this constant pullup.

Diagram (c) and (d):

Q1: What is advantage of (d) over (c)? The book mentions the following for (c):

This kind of configuration was typical for moderate supply voltages (e.g., 3.3 V) or when the sense amplifiers used for amplification performed more optimally only at common-mode voltage levels below the supply voltage. But as supply voltages go down, and Vt differences due to process variations may significantly affect the performance, this configuration becomes impractical.

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  • \$\begingroup\$ Where are you getting this stuff? We can't answer these questions without some sort of context. \$\endgroup\$ – Dave Tweed Jun 25 '14 at 13:00
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    \$\begingroup\$ I am reading extensively about how SRAM circuitry is implemented (Decoders, Pre-decoders, Sensing Amplifiers and Pre-charging). I am using various sources. The above data is from Book: "Memory Systems: Cache,DRAM,Disk." \$\endgroup\$ – shingaridavesh Jun 25 '14 at 13:12
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It mentions it as diode-connected NMOS pair. Why?

Consider the following connection topology of a bipolar transistor where the collector and base of the transistor are short circuited.

schematic

Clearly this resulting 'two-terminal' device acts as a diode. And hence it was named as 'diode connected' transistor.

When the similar configuration was implemented with field effect transistors, the same name was used.

The \$I_C\ vs\ V_{BE}\$ and the \$I_D\ vs\ V_{GS}\$ graph justifies the same.


Q2: This burns more power during write operations where one of the bitlines is pulled low by the write amp, again fighting this constant pullup.

The circuit in (a) is diode connected and hence the NMOS will be in saturation (Vdd > Vt assumed) and hence this would always try to pull up the bitlines to Vdd.

For writing a '0', BL should be pulled down to GND but extra power would be needed to pull down BL because the NMOS is trying to pull it up. Similarly, for writing '1', BLB should be pulled down to GND.

Or,

While writing, the write amplifier will be trying to pull down the bitline (BL or BLB) to GND. So there will exist a low resistance path from Vdd to GND. This will cause more current to flow through the circuit increasing the power dissipation.


What is advantage of (d) over (c)?

The obvious one is that (d) requires less number of transistors.

The diode connected NMOS causes a drop of Vt across it. Now this Vdd - Vt should be capable of switching the transistors below. So The supply voltage can not be reduced beyond a limit in this circuit. Hence this configuration can be used for moderate supply voltages. Where as configuration in (d) can be used for smaller voltages.


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  • \$\begingroup\$ In the case of MOSFET when Drain is connected to Vdd and Source is at GND and Gate is also at Vdd, then wouldn't there be saturation and pinch off condition. So above will always works in saturation? \$\endgroup\$ – shingaridavesh Jun 26 '14 at 3:31
  • \$\begingroup\$ @shingaridavesh Saturation will happen only if the Vdd is above threshold voltage. Similar to diode where the conduction happens only when the voltage across it is more than forward cut-in voltage. \$\endgroup\$ – nidhin Jun 26 '14 at 10:30

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