# Initial states in a digital system with more than one stable state

Let's say I have a digital system of basic combinational logic with feedback (I do). That is, the value of the gates' inputs depend in some way on the value of their outputs.

Depending on the system, particular combinations of gate inputs would be unstable, meaning that the outputs of the gates, when they have that particular combination of inputs, would propagate through the feedback path to the inputs and change the set of inputs to a different state. This is what makes a state unstable: the fact that the system cannot remain in this state any longer than the time it takes for the signals to propagate through the feedback path and back to the inputs.

Now, let's say my system has only two stable states, with the only difference being in the state of a single input (let's call it input A). If A is 0 (and all of the other inputs are in their "proper" configuration to be stable), the system is in stable state 0. If A is 1 (and all other inputs are properly configured), the system is in stable state 1.

When I power up the system, is it equally likely to settle in stable state 0 or 1, or is it more likely (or perhaps certain) to be in one or the other due the way the initial power supply curve upward to +5V (and downward to 0V?) affects the logic ICs?

Is there a way to predict which state will be the initial state by just considering the construction of the system?

Is there a way for me to influence the initial state without changing the fundamental structure of the system? For example, could I possibly use a type of pullup or pulldown resistor on input A, so I could set an initial state of +5V or 0V at A, but then allow the feedback from the other gates to control the state of A at all points after time zero? (I'm imagining the resistor setting the voltage would happen slightly before the CMOS ICs are powered up and working to set the voltage).

I imagine that dealing with initial states is a pretty common issue, and that there's probably a pretty standard way to do this.

## 3 Answers

Instead of an RC reset circuit, you might want to consider a microprocessor supervisory circuit such as the Micrel MIC1810. It generates a 100 ms reset pulse on startup, and whenever VCC falls below a set threshold (so it functions as a BOD also). Although designed for microprocessors, it may work in your application also.

• It looks like this is designed for 3.3V systems. Would it still work correctly on powerup for a 5V system? Commented Mar 22, 2011 at 14:19
• @JoeMac, yes, I forgot to note you were using 5v logic. You want the MIC1810 instead of the 1815. I have modified my answer. Commented Mar 22, 2011 at 17:40

In digital electronics, the initial state is usually defined as the reset state. When the reset signal is active, the state is forced to a predefined value.

The reset signal is active when the device is powered on. Often, '0' (or low voltage) is used to mean an active reset signal. As a capacitor charges, the voltage of the reset signal rises and the reset signal becomes inactive.

Take a look at the D-flip-flop on the Wikipedia for an example: http://en.wikipedia.org/wiki/Flip-flop_(electronics)#D_flip-flop

• What about BarsMonster's concern that the capacitor charging will not work if the powerup curve is too slow? Also, how is a D-type flip-flop an example of a device with a reset state? In all my tests, the Ds I have always have started up in the last state they were in when the device was last shut down, rather than in one particular state or the other. If they did start in one particular state, they would be fit to provide a reset signal but this is not the case. Commented Mar 22, 2011 at 14:12
• @JoeMac: I think what Philippe meant to say is that a D-type flip-flop is an example of a device with more than one stable state, similar to the original poster's circuit. It's not intended to output a reset signal; it has a reset input signal that can be used to briefly override the normal functionality at power-up. Commented Dec 15, 2011 at 15:51
1. Pull-ups might work, but they will constantly eat power

2. You may use capacitor to VCC - so that during powerup you'll get a short pulse, but it most cases power rises quite slowly...

3. Just make reset signal, which resets everything to required state, and add BOD scheme to autoreset on powerup after vcc reache level of stable operation.

4. You may design the system so that 0V on all gates is default state - you will have to invert things in many places to do so... This is gonna be tricky :-)

• (2) Are you saying that a capacitor scheme will likely NOT work with a slow-rise of power? (3) Can you explain or link to an explanation of "BOD"? (4) Are you saying that 0V is the default state when powering up? Commented Mar 18, 2011 at 16:09
• I think he's talking about brown-out detection. The initial state(s) would be held until the supply voltage reaches a minimum level (or is above a level for a certain period of time) then the initial state(s) are released. Commented Mar 18, 2011 at 16:25
• Implementing a detection scheme like that seems to be a little too complicated for my purposes. Maybe I'll just take the pullup resistor power hit. Commented Mar 18, 2011 at 16:59
• Yes, BOD = brown-out detection. With slowly rising power (microseconds) pulse after capacitor would not be powerful enough to trigger your circuit. Commented Mar 18, 2011 at 18:18