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I was unable to understand two parts of a circuit in a magazine, where you can see a resistor R4 and a cap C8 to ground for—I guess—debouncing purposes, but can't see how it works.

RC debouncer

The other one is another resistor and cap to ground, the switches are already set for configuration before the circuit is up, it's basically just interrupting the output of the CD4017 to initiate the cycles, but can't see why using this parallel RC configuration here C9 - R9.

enter image description here

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  • \$\begingroup\$ Since there is a resistor in parallel with the cap, the voltage rise, for practical purpose, is instant. After the cap charges and the switch opens the discharge is through the 10k resistor in a series circuit hence all LPF reason applies. \$\endgroup\$ – user34920 Jun 25 '14 at 21:36
  • \$\begingroup\$ So how and when the voltage arrives to the NAD gate , can't see any any series circuit , and can't see how it can be a LPF \$\endgroup\$ – Blu3sy Jun 25 '14 at 21:49
  • \$\begingroup\$ I was actually referring to the 1st picture, the second one I'm not sure about. Andy aka suggested a possible explanation for that one in his answer. Not sure much is possible without digging further into the circuit. \$\endgroup\$ – user34920 Jun 25 '14 at 21:53
  • \$\begingroup\$ I don't want to know what a NAD gate is, but I wonder if the NOR gates are Schmitt-trigger input types. \$\endgroup\$ – Spehro Pefhany Jun 25 '14 at 23:16
  • \$\begingroup\$ It's NOR gate , sorry for that misleading comment , actually it's connected to a monostable & then to a gated SR Flip Flop, this is an emergency push button , so it's designed to be really sensitive i guess \$\endgroup\$ – Blu3sy Jun 26 '14 at 13:49
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Ignoring the resistor, when the switch initially closes, the voltage on the cap charges fairly quickly - limited by the power supply and its local decoupling capacitors, the resistance of the switch and any track resistance and inductance. If the switch momentarily went open circuit, the cap would stay largely charged. This means you get a slightly delayed (maybe 10 - 100 us delay) pulse edge and the cap stays charged even if the switch opened and closed a few times. It doesn't jump up and down because the only discharge path for the cap is via the 10k resistor.

In short you get one rising edge with an initial delay of 10 - 100 us after the switch is first pressed. When the switch is released the 10k discharges the cap in about 5 *CR = 5 milli seconds.

There won't be multiple edges generated and that might be important. As for the 2nd circuit I suspect they want the signal "held-up" for a few milliseconds after the drive from the other chips have disappeared - I suspect this is a timing issue or design fix.

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  • \$\begingroup\$ Thanks Andy ,so after a delay of 10-100 us is when the cap is fully charged and that a pulse arrive to the NAND gate ? \$\endgroup\$ – Blu3sy Jun 25 '14 at 21:44
  • \$\begingroup\$ @Blu3sy the rising edge in uninterrupted by the cap as the voltage is across the resistor. BTW where is the nand gate? On the 1st picture is seems like a NOR. \$\endgroup\$ – user34920 Jun 25 '14 at 22:01
  • \$\begingroup\$ It is a NOR sorry for that misleading comment , thanks for your help \$\endgroup\$ – Blu3sy Jun 25 '14 at 22:10
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I think the 10K resistors to ground are primarily pull-down resistors to ensure that the gate input is low when the switch is open. Any effect on the "debounce" function of the capacitor is incidental.

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