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I used Xilinx to simulated Logic And Gate, and it worked fine. I followed same procedure to simulate Half-Subtractor, but got stuck in between.

When I checked Xilinx window for two codes I found two differences (please see red boxes in the following figures).

Correct one

Above program worked fine without any problem.

Simulation Error

Can anyone check my figure and find out where I went wrong?

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  • \$\begingroup\$ Perhaps you could express any warnings or error messages produced? It isn't readily apparent whether you are talking about simulation or synthesis from the two images. If it's simulation you'd expect that any problem might stem from your entity being unbound. Half-Subtractor is not a legal VHDL identifier. Analysis should have failed - try substituting an '_' for the '-' in the entity name. \$\endgroup\$
    – user8352
    Jun 26 '14 at 6:46
  • \$\begingroup\$ The code that I wrote is not even detected as VHDL (I think). To check syntax the code should come under module like in first code. \$\endgroup\$ Jun 26 '14 at 7:02
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Without resorting to what Xilinx is reporting in their GUI, your VHDL code is not valid. "Half-Subtractor" is not a valid entity name:

token_test Half-Subtractor 00001 IDENTIFIER_TOKEN (128) Half 00001 DELIM_MINUS ( 14) - 00001 IDENTIFIER_TOKEN (128) Subtractor

An identifier in this context is a basic identifier:

basic_identifier ::=
letter { [ underline ] letter_or_digit }

And a minus sign delimiter is not allowed.

Your entity name comprised of two identifiers separated by a delimiter. Running into the minus sign token then another identifier before the reserved word is will guarantee it won't analyze, it will fail in the entity declaration:

 entity_declaration ::=
      entity identifier is
          entity_header
          entity_declarative_part
  [   begin
          entity_statement_part ]
      end [ entity ] [ entity_simple_name ] ;

Where entity_simple names should be read as entity_simple_name, a predicate tested simple_name for the entity that must match the declared name.

If it doesn't analyze it doesn't show up. If it didn't analyze that should show up somewhere as an error, and that it isn't bound could get reported as well.

Change from:

entity half-subtractor is
end entity;

Which get's an analysis error along the lines of:

ghdl -a half-substractor.vhdl half-substractor.vhdl:2:12: missing "is" after identifier half-substractor.vhdl:2:12: (found: -)

telling you the syntax is non-conforming, to something conforming to the VHDL standard:

entity half_subtractor is
end entity;

and:

ghdl -a half-substractor.vhdl

(Analyzes without error).

Your view of what is happening here appears to be obscured by all the visual noise provided by the GUI. Somewhere Xilinx's tools should be telling you your VHDL is syntax deficient besides not showing up as elaborated in some little window pane.

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It looks to me that 'subtractor' is not properly added to your project. Try to create a new project and then add a new VHD module to the xa3s50-4vqg100 (right click on xa3s50-4vqg100). Then, place your code in it.

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