I am working with a low latency 10G MAC IP core for a Stratix V FPGA. One of the parameters is "High performance mode". The documentation states

When enabled, high performance mode enables all retimers, which allows for high timing margin, but horrible delay.

What are retimers? How are they implemented in FPGA? How do they affect timing margin and delay?


'retiming' logic usually refers to inserting pipeline stages to make timing constraints. From your description, some of the pipeline stages are made optional controlled by this parameter.

If you can't close timing in the area of this core, enable it.


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