I have a very fast clock called
CLOCK_50 which I would like to slow down through the use of a clock divider. The output is
clock. I also want to use a two-stage synchronizer for an asynchronous reset port
reset0 which should output
reset into the core. However, I'm not sure how to get these to work across different clock domains.
This is what I came up with. It generated several errors when compiled.
logic clock, reset1, reset2, reset; logic [13:0] countCLK; always_ff @(posedge CLOCK_50) begin reset1 <= reset0; reset2 <= reset1; reset <= reset2; end always_ff @(posedge CLOCK_50 or negedge reset) begin if (!reset) begin clock <= 1'b0; countCLK <= 14'b0; end else begin if (countCLK) clock <= ~clock; countCLK <= countCLK + 14'b1; end end
And the warnings:
Warning (308040): (Medium) Rule C104: Clock signal source should drive only clock input ports. Found 1 nodes related to this rule. Warning (308010): Node "clock" Warning (308027): (Medium) Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized. Found 1 node(s) related to this rule. Warning (308010): Node "reset"