Async FIFOs are characterised by their static latency, expressed as a number of complete cycles in the source domain (before the crossing) and in the destination domain. The crossing itself introduces jitter if there is not an exact phase and frequency relation between the two clocks. In your example you say the phase wanders, for this to happen the clock frequency must be slightly different. You are correct that this introduces 0-1 extra cycles on top of the static latency, depending on if the asynchronous grey-code counter signals land ahead of the setup window (0) or fall into the next cycle (+1).
Static values for the dcfifo megafunctions are in the Quartus Megafunction GUI and depend on the parameters you've set - otherwise you can measure see them in simulation. I think it's 1 cycles before, 2 cycles after, so 3 static in the show-ahead mode, so overall 30-40ns for your case.