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Although there are many similar questions to this one, I wish to get your attention to this specific board layout.

The main power on the board will be 5V, and one of the layers is dedicated for this. However, the board will be connected to a 12V power, so I am using an LDO to drop the voltage to 5V. Keeping in mind current flows, the ideal placement of the LDO would, probably, be at the center of the board, however, I placed it on the top left (see the bottom plane layout).

  1. Is this acceptable placement or there is a better way in this case? Maybe I should route a fat trace in the power/ground planes to the center of the board, so all the currents spread/return from/into the center like on the figure below? Should the ground from the 12V connector and ground LDO pin originate from the same point, or it's ok to connect them to ground plane at different points?

    enter image description here

  2. Is it useful (in my case) to have some ground plane islands on the top and bottom signal planes in addition to the separate ground plane layer, or should I limit the top copper plane to only certain areas? My biggest concern is bypass caps and GND pins connection. I did try to place the components so the negative pins go outward and connect to the larger top GND plane areas. However, would it not be better to place via right next to the GND pins so they connect directly to the GND plane layer?

  3. Speaking of GND via: I tried to place them close to several ground pins at once to make a local GND 'star' connections. Again, would it be better to use more GND via at each GND pin, or that is unnecessary? Does it considerably increase the manufacturing price?

  4. I also tried to spread additional GND via equally spaced across the entire board area. Is it a good practice? How is the efficiency vs. manufacturing price?

  5. Should I make a small split in the GND plane layer somewhere between the ADC and a SN74 buffer? So to say I separated digital and analog grounds?

  6. Please, comment on how I could improve my current PCB layout.

Additional info:

  1. Planes: Signal, GND, Power, Signal
  2. Main power: 5V and additional small LDOs (3.3V, 1.8V) designated with the letter V.
  3. Sampling: 10MHz, oscillator 40MHz.
  4. To the left: CPLD, small uC.
  5. Center: linear imager.
  6. To the right: OpAmp, Diff Amp, ADC, SN74 buffer (bottom to top).
  7. Buffer gates designated with the letter G.
  8. I will remove small unconnected islands of copper at last.

TOP

GND

POWER

BOTTOM

This is a combined image of TOP and BOTTOM planes:

enter image description here

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    \$\begingroup\$ Why do folk call a low-drop-out regulator "LDO". It doesn't just apply to this question because I've seen it phrased this way on a few questions. BTW your regulator doesn't need to be an LDO type because your input voltage - output voltage is large enough to suit a 7805. What current is taken from the 5v regulator? \$\endgroup\$ – Andy aka Jun 28 '14 at 16:24
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    \$\begingroup\$ @Andyaka Ideally, it should not take more than 0.8A. I did not think too much about the DC/DC conversion. Why would I benefit more from LM7805? Even if I did not need power converter and supplied the board with 5V directly, My concern was more about where to place the origin of power/gnd on the board. \$\endgroup\$ – Nazar Jun 28 '14 at 16:32
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    \$\begingroup\$ I didn't say you would benefit more - I just said it doesn't need to be an LDO type and exactly the same power would be dissipated because, I believe "LDO" is a term that applies to linear regulators. Regards the rest of the question, it was too long for me to take in all at once but, in the absence of a circuit, I summised it could be tricky to do a good answer so I thought I'd moan n groan about usage of terms instead LOL. \$\endgroup\$ – Andy aka Jun 28 '14 at 16:42
  • \$\begingroup\$ 0.8A means your PCB is going to be dissipating about 10W, in about 3" square(?). That's going to be "interesting". I estimate about 80°C rise if you mount the board vertically and it has reasonable (\$\sqrt[4]{3}\$ ~= 1.3") space on either side. \$\endgroup\$ – Spehro Pefhany Jun 28 '14 at 17:17
  • \$\begingroup\$ @SpehroPefhany My apology, I did not say it correctly. I meant 0.8A @ 5V and hope it will not go over 0.5A. I am not as experienced to consider temperature characteristics of a board, but now I will keep it in mind. \$\endgroup\$ – Nazar Jun 28 '14 at 18:07
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I'm not sure that I know the best way to build the board, but I know what I would do.

  1. The location of the 12V-to-5V regulator, whether linear or switching, will not matter. The corner of the board is fine.
  2. I would not bother with filling either top or bottom of the board with ground planes. The impedance of the signal traces is defined by the internal planes, not the extra copper you pour on the outside. The extra coper isn't shielding internal signals, all that is underneath are power and ground planes. Instead, connect ground and power pins of components directly, as close as possible to the pin, to the planes.
  3. Don't share power and ground vias between different devices. One via per pin minimises noise on the pin and routing distance to the ground plane. If you are so worried about the manufacturing price that a few vias are going to be significant, you must be shipping in very high volume, so you can prototype a dozen different layouts to optimise it. If this is a one-off, the biggest cost risk is that you don't get it right first time, so be conservative and use lots of vias.
  4. Put a via by every component ground pin (not necessarily every component signal pin that happens to need routing to ground). Minimum noise on power and ground planes comes from effective decoupling. High frequency noise is minimised by using physically small ceramic capacitors and keeping the power and ground vias close together - underneath the capacitor, if possible. The cross sectional area of the loop from power plane up through via to capacitor, along capacitor and down through via to ground plane, places the lower limit on how effective the decoupling is.
  5. I would definitely not put any splits in the ground plane. Instead, if there are analog signals sensitive to noise, I would not route digital signals close to them. I would try and keep those sensitive analog signals just on the top layer if possible, no vias to the bottom at all. If I can isolate an area of sensitive connections all together on the top layer, I would route a single loop of trace all round there on the top layer, and connect that loop at one point with a via to the ground plane. That approach has worked well for me in the past with very sensitive signals.

And finally: it is conceivable that some clever technique of sharing ground connections might help noise in the analog wiring, but you'd need to know the exact circuit and think very hard about it to be confident. These rules of thumb have worked pretty well for me.

Good Luck!

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  • \$\begingroup\$ I do not understand how would you route a single loop of trace all round there on the top layer, and connect that loop at one point with a via to the ground plane. Could you expand on that, please? \$\endgroup\$ – Nazar Jul 2 '14 at 14:12
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    \$\begingroup\$ A sensitive analog connection is one that could be disturbed by coupled noise from other traces. For example, a virtual earth input on a high speed opamp. If it's possible, route all the wire of that connection on the top layer. Then route a signal trace in a loop, all the way round the outside of that connection, not touching it, and ground that signal trace with a single via. The loop reduces coupling to the sensitive connection from any nearby traces on the top layer. \$\endgroup\$ – emrys57 Jul 2 '14 at 15:28
  • \$\begingroup\$ Do you mean surround the signal traces and pads with ground traces or a ground isle? \$\endgroup\$ – Nazar Jul 2 '14 at 15:45
  • \$\begingroup\$ The traces of the analog signal are on the top layer only and stretch across the board from the bottom up to the ADC (U5 top plane). Speaking on loops: I was always told to avoid creating loops. Wouldn't routing the signal trace in a loop cause a problem? \$\endgroup\$ – Nazar Jul 2 '14 at 15:57
  • \$\begingroup\$ If you have long analog traces, then routing loops around them isn't going to be practical. I was thinking of a few small components close together. Alternating magnetic field can induce currents in loops and thus cause voltage differences along the loop, so are bad for signals. Because the shielding loop is not used for signalling and has only one via to ground, that does not matter. \$\endgroup\$ – emrys57 Jul 2 '14 at 16:09
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I think the general practice should be to maintain a solid plane where possible, and then place noisy components near the periphery so they don't contaminate sensitive nodes.

You can place your LDO wherever you want if you are going to put it's output to the plane. The periphery, near the 12V header might be a natural place for it. Be sure to strap it to the plane well with plenty of vias.

Conversely, you can put 12V in the plane, and the get your LDO 5V at the few points you need it with thick top copper.

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