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I'm working through the open Nand to Tetris course offered by Nissan and Schoken. I've just finished chapter 5, where we construct a 16-bit computer using a hardware description language and an instructor-provided hardware simulator.

Building a Modern Computer from First Principles - Nand to Tetris course

The CPU that we build for the computer uses three clocked components: a program counter, an address register, and a data register. You can see a diagram of the CPU on page 94 of the PDF below, and a diagram of the whole computer on page 97:

Chapter 5 - Computer Architecture

The output of the program counter connects to an external ROM which instantly outputs the instruction at the address specified by the program counter. If the outputted instruction is a "set address" instruction, it propagates instantly to the CPU address register, where it will be stored on the next falling clock edge.

My question follows. Both the program counter and the address register are clocked components. They are connected in series, with the output from the program counter feeding (eventually) to the input of the address register, like so:

 ___________________      _____________        ____________________
|  program counter  |    |  ROM 32K    |      |  address register  |
|         ^         |--->|             |----->|         ^          |
|___________________|    |_____________|      |____________________|

In a physical implementation of this circuit, how could I ensure that the ouput from ROM 32K would be stored successfully in the address register? Both components update on a falling clock edge. Imagine that the falling edge signal takes .2 clock cycles to reach the program counter, update it, and then propagate through the ROM, but takes .8 clock cycles to reach the address register. In this case, the output from the ROM would change before the falling clock edge reaches the address register.

The hardware simulator in our class solves this problem by storing new component states on falling clock edges and then propagating the new component state on rising clock edges. This ensures that component component B can capture component A's output before component A outputs a new state. I was wondering how this problem would be solved in a physical implementation.

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  • \$\begingroup\$ The ROM has an internal delay as well. \$\endgroup\$ – Ignacio Vazquez-Abrams Jun 28 '14 at 17:09
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The address register can be clocked on the same edge as the program counter, depending on the setup and hold times of the blocks involved. Some parts have a zero or even slightly negative hold time, meaning you won't need to worry about the minimum propagation delay of the counter and ROM. Otherwise you have to ensure that the output of the ROM is stable for the hold time requirement of the register, as well as that it is stable in advance of the edge by the setup time requirement of the register.

Of course, in that case, the register clocks in the value that had a read initiated on the previous clock edge.

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  • \$\begingroup\$ Thank you. This helped. Also, I googled some keywords from your answer and came up with a powerpoint that explains in depth:web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/… To be sure I understand: There is a built-in propagation delay for each component. This means that the ROM will maintain its output for some time period (less than a clock cycle) after the program counter has updated. The address register can capture the ROM output during this period. Is that a correct restatement? \$\endgroup\$ – BitPusher16 Jun 28 '14 at 18:16
  • \$\begingroup\$ @BitPusher16 Capture occurs at a clock edge (and the input signal must, in general, be there and be stable a bit before and a bit after the clock edge). Say the clock is at t = 1usec, the register might require that the signal be there at t= 1usec (and no later) which is 0ns setup time, and be maintained for 100ns (100ns hold time) after that for it to be guaranteed to be read correctly. The ROM output will be stable after the input signals are stable, plus the propagation delay. So long as that meets the requirements you're fine. \$\endgroup\$ – Spehro Pefhany Jun 28 '14 at 18:30

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