I have to design a power supply with the LTC1707. It have a enable input to control it. Now I have to enable an disable this switching supply with a push button.

Only when I push in button during five second, enable = 1. And if I push a button during five second again, enable = 0.

I have made a schematic with a Flip Flop, but it is instantaneous, i need five seconds. Is it possible to make this function without microcontroller ? Do you have any idea?

Thanks, sorry for my english...


Thanks a lot for your help! After some research and test on Proteus, i have made a smallest schematic ! :


  • \$\begingroup\$ Welcome! It's not clear (at least to me) what you mean- whether you intend to hold the switch for five seconds or what. Could you link to a timing diagram or similar? \$\endgroup\$ Commented Jun 30, 2014 at 14:45
  • \$\begingroup\$ I think he means that pressing the button for at least five seconds turns on or off the power supply. And yes, that's feasible without a micro, but you will need something to power the timing circuit. \$\endgroup\$ Commented Jun 30, 2014 at 14:56
  • \$\begingroup\$ Yes it's exactly what I want Vladimir Cravero ! The power supply is power by a lipo battery, so i can power the timing circuit with the lipo to control power supply! But i don't know how to make the timing circuit for this application ! \$\endgroup\$
    – user46510
    Commented Jun 30, 2014 at 15:08
  • \$\begingroup\$ @user46510: What's your battery input voltage? \$\endgroup\$
    – EM Fields
    Commented Jul 1, 2014 at 4:14
  • \$\begingroup\$ Is the switch normally open or normally closed? \$\endgroup\$
    – EM Fields
    Commented Jul 1, 2014 at 18:06

1 Answer 1


This should work:

If you have some glue logic you can use for U2, use that. If you don't, D1 D2 R5 will do the same thing.

enter image description here


S1 is a single-pole single-throw normally open momentary switch, U1A and U1B are the two halves of a dual monostable multivibrator, U2 is an AND gate, and U3 is a "D" type flip-flop.

When Vcc is first connected, U1 and U3 will be held low by C3, resetting them until C3 charges up through R4 and goes positive enough to release the resets.

When that happens, U1A-Q, U1B-Q, U2-3, and U3-Q will all be low and will remain that way until S1 is made.

When S1 is made, U1A-A will go high, triggering U1 and forcing U1A-Q high for the time set by R2C1, about 5 seconds.

When U1A times out and U1A-Q goes low, that edge will trigger U1B, forcing U1B-Q high for about 100 milliseconds. Then, if S1 is still made when U1B-Q goes high, U2-1 will also be high and U2-3 will go high until either U1B-Q times out or S1 is opened.

U2-3 is connected to the clock input of U3 and, when it goes high, will toggle U3-Q since U3 is wired as a divide-by-two.

With U1A and U1B both timed out, when S1 is opened U1A-A and U2-1 will go low, returning U1 and U2 to their initial states.

If, subsequently, S1 is made and held made for the time it takes U1A and B to time out, U3's clock input will be exercised and it will once again toggle, completing the cycle.

  • \$\begingroup\$ I can't tell why easily. Why does this work and what ICs are the first two feeding the AND gate? \$\endgroup\$
    – sherrellbc
    Commented Jul 1, 2014 at 1:50
  • \$\begingroup\$ See the edited article. \$\endgroup\$
    – EM Fields
    Commented Jul 1, 2014 at 4:08
  • \$\begingroup\$ I've not worked with 4538 chips before (and am new to EE in general). Do the RC circuits that control the timing discharge through it? Otherwise I would think that a series of taps would also turn on this circuit, as long as the accumulated time held down equals the 5 seconds. \$\endgroup\$ Commented May 20, 2016 at 21:00
  • \$\begingroup\$ @DavidWoods: Here's the 4538 data sheet which will answer your question. What do you mean by "a series of taps"? \$\endgroup\$
    – EM Fields
    Commented May 20, 2016 at 22:07
  • 1
    \$\begingroup\$ @DavidWoods: Here's a better [data sheet] (cache.nxp.com/documents/data_sheet/HEF4538B.pdf) which clearly shows - in Figure 2 - the relationship between the RC and the trigger. Note that the the timing cap is quiescently charged to Vcc and the timeout starts when it's discharged to ground. Note also that trigger inputs are level sensitive, not edge sensitive, so it's conceivable that your "series of taps" scenario could be played out, but the reservoir would have to be emptied between hits in order for the scheme to be viable. \$\endgroup\$
    – EM Fields
    Commented May 21, 2016 at 12:06

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