I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this module are multidimensional arrays. For example:
input signed [15:0] data_x [3:0][1:0],
data_x is a 3 dimensional vector.
For a vector such as
input signed [15:0] data_y,
to define the input delay, the constraint would be
set_input_delay -clock [get_clock clk] 5000 [get_ports data_y\[*\]]
However, for a multidimensional array input, the following wildcard setup does not appear to match the inputs:
set_input_delay -clock [get_clock clk] 5000 [get_ports data_x\[*\]\[*\]\[*\]]
The following works, but matches other internal signals in the design( such as
data_x_d, which is undesirable):
set_input_delay -clock [get_clock clk] 5000 [get_ports data_x*]
Is there a way to specify the name with a wildcard to correctly identify all ports in a multidimensional array?