Is it more energy efficient to have active high or active low pins (I'm thinking shutdown, reset, active type of pins)? Pins that one would not expect to change very often so they will be in one state for a while before transition.
I'm looking at this from a hardware perspective, does a 1 or a 0 cause a greater voltage drop (ie less efficient). I would think this depends on if the underlaying hardware was implemented as a P (PNP, PMOS) or N (NPN, NMOS) based device. After reading this post, it seems that if the hardware is PMOS it is better to have it be active low because when it is in a low voltage state the current flows therefore creating a voltage drop. And for NMOS circuits it would be better for it is be active high because that is when current would flow.
Is this a correct analysis?