# More Energy Efficient 1 or 0

Is it more energy efficient to have active high or active low pins (I'm thinking shutdown, reset, active type of pins)? Pins that one would not expect to change very often so they will be in one state for a while before transition.

I'm looking at this from a hardware perspective, does a 1 or a 0 cause a greater voltage drop (ie less efficient). I would think this depends on if the underlaying hardware was implemented as a P (PNP, PMOS) or N (NPN, NMOS) based device. After reading this post, it seems that if the hardware is PMOS it is better to have it be active low because when it is in a low voltage state the current flows therefore creating a voltage drop. And for NMOS circuits it would be better for it is be active high because that is when current would flow.

Is this a correct analysis?

• I prefer to Pull it down(if no other Pull up/pull down internally exists) for it's noise immunity(If noise want to change the state of an IO, it needs to pull it up by giving more current, because generally noise is very weak signal it will not have enough strngth to Pull that pin High – user19579 Jul 2 '14 at 6:50
• I think that argument is fully symmetric, so it can't be used to select between pull-up and pull-down. – Wouter van Ooijen Jul 2 '14 at 7:11
• @user19579 I don't see how noise can be "strong enough" to pull a pin down instead. – Vladimir Cravero Jul 2 '14 at 8:14
• @VladimirCravero That could be possible if you have very very weakly supplied outputs but where when low they become shorted to ground – Vality Jul 2 '14 at 12:29
• well that's kind of my point: there's no noise related difference on pulling pins down or high. – Vladimir Cravero Jul 2 '14 at 12:43

It's completely symmetric and thus, in the terms your looking at it, irrelevant. Note that I wrote the long post you refer to above. The polarity of control signals are more about how much external logic is needed to enable them. If you have negative logic then a wired Nand approach with an internal pull up and no external logic makes sense.

Other elements that come into play are power rail ramp up, boot up of the chip and indeterminate states of the chip whist the power is ramping. And this is really about the configuration of the logic, threshold values and switch points. I tend to design systems that always come up in a reset state even before the rest of the circuit can possibly come alive, and only when the rest of the chip has come alive do I allow the reset to be deserted. But not everyone does this and you might see chatter and activity before a forced reset and then clean boot up. Which might be fine.

Clarifying my symmetric comment. I wouldn't read too much into the advantages of PMOS vis-a-vis NMOS with this regard as the drain of the NMOS can leak towards the upper rails just as easily as the drain of the PMOS can leak towards the negative rail. You really need to look at individual designs, processes and details . A generalized statement doesn't work and more over is not useful.

If you are concerned about efficiency then you'd be best at controlling the edges (or rather the number of edges), that's when CMOS burns energy.

Back in the stony ages, (I know - I was there) when vacuum tubes were used to build digital circuits, their input structures (control grids) were pulled low quiescently in order to keep the first stage cut off and conserve power, so in order to effect control of the circuits the inputs were implemented as positive true logic.

Later on, when Texas Instruments first introduced their hugely successful 7400 series of TTL digital logic, the inputs were the emitters of NPN transistors whose bases were connected to the positive supply rail through about 4 kohm resistors, the main reason being that, doing it that way, many emitters could easily be pulled low through the NPN common-emitter part of an output's totem-pole, and in the bargain, get better noise immunity than if the input were a base pulled to either rail through a resistor. The result of all that was that TI's control inputs became negative true and defaulted to unasserted with those inputs floating or connected to Vcc.

Then, when RCA came out with their CD4000 line of CMOS logic, the inputs were floating gates so there was no particular advantage to having either low or high true inputs. Philosophically, though, RCA was an old, established tube maker, and their conventions made it over into their CMOS line, with the result that most of their 4000 CMOS came out with positive true inputs.

Fast forward to today, and we now have the CD4000 family logic functions implemented in 74HC as well as in the traditional higher-voltage line, so we get to pick and choose between high-true and low-true, pretty much as we see fit.

• Good reminder regarding static power consumption in TTL and CMOS – Dirceu Rodrigues Jr Jul 2 '14 at 15:24

placeholder answer is great, I'd just add my idea about why you usually find enables, chip selects and such all active low. We understood that internal circuitry is CMOS so power consumption does not really have a role around here, then why is that? There's two reasons in my opinion:

• Power on: when you turn on a device the ground reference is likely to stand still$^1$ while power busses would ramp up. That might lead to glitches in the logic value of the inputs, while during power on keeping thinks still is a good idea
• Routing easiness: on a two layer or single layer PCB you are more likely yo have a ground plane lying around, connecting a pin to ground would then be much simpler, through a pull down or directly.