How does assignment through a contribution statement (statements with <+ operator) works in verilog-a?

I read in the language reference manual of verilog-a the following about the branch contribution statement:

The simulator adds the value of the right-hand side (of contribution statement) to any previously retained value for the branch for later assignment to the branch. If there are no previously retained values, the value of the right-hand side itself is retained.

Could anyone explain to me how this method assigns proper values for the branch current or voltage?


1 Answer 1


This can be explained with the help of the following example:
analog begin V(in) <+ 2; V(in) <+ 3; end
Initially the simulator sees the value 2 and assigns it as a voltage of port in. Then it sees the value 3, but the simulator will add the previously stored value for in i.e., 2 to the present value so final value assigned will be 5V.


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