How does assignment through a contribution statement (statements with <+ operator) works in verilog-a?
I read in the language reference manual of verilog-a the following about the branch contribution statement:
The simulator adds the value of the right-hand side (of contribution statement) to any previously retained value for the branch for later assignment to the branch. If there are no previously retained values, the value of the right-hand side itself is retained.
Could anyone explain to me how this method assigns proper values for the branch current or voltage?