# How to simulate PCIe to debug my FPGA endpoint

I'm working on an FPGA controller connected through PCIe. The only way I can debug the hardware is using chipscope. So I execute commands through my driver and check out the signals from the FPGA.

The problem is that it takes a lot of time to build the project and load it to the FPGA every time I want to check a signal to debug the project.

Is there an easier way to debug an FPGA connected to PCIe?

Is there a way I can simulate all the PCIe signals and not have to run the FPGA at all?

To be more specific, I would like some kind of infrastructure that I can write a command through the linux driver (writeq) and TLP packets would be sent to my verilog design..

The best way to achieve this depends on your driver. For example I've done something similar for a userspace mmap based driver: source code is available on Github. If you want to co-simulate kernel drivers you may want to investigate QEMU or similar. Alternatively you could mock the kernel calls.