Sometimes the FPGA manufacturer recommends a fanout pattern and capacitor placement pattern.
Have you looked at the datasheet for the chip you want to use for capacitor placement information?
Have you looked at development boards that use that chip?
Often when doing PCB layout I cram all the parts on the board.
Then later -- when laying the traces -- I find out I don't have enough room between the parts to run all the wires.
In particular, fine-pitch components like TQFPs need a lot of room around them to "fan out" their wires, sometimes more room than I expected. (PCB layout artists find it requires even more resources to fan out BGA packages).
I generally end up spreading the wires apart something like this,
to give myself plenty of room for capacitors and via patterns and other kinks in the wires between the components:
(image from FPGA-Based Retrocomputing http://www.fpgaretrocomputing.org/pdp10x/ )
I typically end up with capacitors on the same side of the board as the chip, with the +VDD end of the capacitors pointing directly at the chip,
and the GND end of the capacitors pointing away from the chip,
as in figure C of " Best place to place a decoupling capacitor ".
Occasionally I end up with capacitors on the same side of the board as the chip,
with the capacitors going "across" the fanned-out traces, as in C19 in the top image at "
Decoupling caps, PCB layout ".
(But as I said before, more often like C17 in that image).
This generally means capacitors left and right of the chip are horizontal,
while capacitors above and below the chip are vertical.
However, sometimes it is convenient to have capacitors near the corners placed diagonally,
like several of the capacitors connected to pins near the upper-left corner of this Xilinx FPGA:
(from http://www.summitsoftconsulting.com/UsbAnalyzers.htm ).
Some BGA packages force us to put capacitors on the opposite side of the board, directly underneath the chip, as described by Peter Bennett.
Since I haven't yet used such high-density BGA components,
I find that keeping all the surface-mount components on the same side of the board typically reduces costs.
I personally find it much easer and takes less time to
leave more space than I really need around TQFPs, and later squeeze everything together,
pack components closely, and repeatedly discover that there's not enough room for the traces, so each time I nudge the components a little further apart.
There are a few cases where bigger capacitors make it easier to lay out the PCB.
When a package has an I/O line, then a VCC line, then an I/O line, then a GND line, then another I/O line --
a bigger capacitor can make a "overpass bridge" from the VCC to the GND line,
and the I/O line can run underneath the capacitor, something like C65 and C61 in this photo:
(image from http://veriest-v.com/index.php?id=16 )