I didn't know whether to place this question here or on stackoverflow, but I finally decided to post it here.

I want to build a simple system that would be able to work with basic peripherals (UART, keyboard, VGA monitor). I would like to use MPU instead of MCU as a ´main unit´, so there would be more memory for processing data. This ´main´ chip would use a single SDRAM to store its data.

For the VGA output, I want to use an Atmel AVR chip, that would request data from another memory, which would contain screen data in 8-bit RGBS format. Here is where I get to problems.

I don't need much of VGA memory (less than 512KB), therefore I want to use SRAM memory, which is also simple to access compared to SDRAM. The VGA resolution I chose uses 25 MHz pixel clock, which means that I have only ~40ns time to retrieve a single pixel from SRAM to DAC. That's good as most of the memories that match my search input (>=4Mbit memory, <40ns access time) can do this.

Back to the MPU memory, I would like to ask my first question: when is it necessary to send a refresh command to SDRAM? Do I have to do it, or is it possible to get a memory that would need any external magic to refresh it?

Now I get to the problem how to access that SRAM VGA memory from the main chip, as it is almost always accessed by my VGA controller (not mentioning that I need yet another chip for mapping this memory nicely to MPU´s address space). I thought of reserving some pins of the VGA controller for MPU´s requests for SRAM access, which would mean that some video frames would have to be skipped leaving this SRAM accessible to MPU without interruptions.

I'm stuck here. I could only think of these possible solutions:

  1. I can use SDRAM on VGA chip instead of SRAM, but I will also need a better controller for the video output. This SDRAM will be compatibile with the one on MPU, and I will need to think about a special tactic for clock stealing, where I could access video memory from the video controller and main processing unit at once.
  2. I can add another chip that will use time when video memory is not accessed (sync pulses, porches etc.) for copying blocks of data from the main memory to video memory.
  3. I can use only one SDRAM memory, and request access to it from the MPU everytime VGA needs another pixel. That would slow down the whole system, but it would be simpler.

What do you think of this? What other ways (tricks, designs?) are here to have two units (main and video processing unit), from which one is being managed by another?


  • \$\begingroup\$ Thanks for your ideas. I gues interleaved memory acccess requires SDRAM, doesn't it? \$\endgroup\$ – user35443 Jul 8 '14 at 19:50
  • \$\begingroup\$ Not necessarily. I have done it with fast SRAM. With 2 chips interleaved, I had more than 2 access windows (I think it may have been 4). By the way, it's much easier to do with an FPGA. \$\endgroup\$ – Tut Jul 8 '14 at 20:04

One thing that used to be common for video graphic controllers is Video RAM or VRAM.

VRAM has two sets of data output pins, and thus two ports that can be used simultaneously. The first port, the DRAM port, is accessed by the host computer in a manner very similar to traditional DRAM. The second port, the video port, is typically read-only and is dedicated to providing a high throughput, serialized data channel for the graphics chipset.

Internally, VRAM reads an entire DRAM row and shifts it out sequentially to the video circuitry. This leave the DRAM available for use by the MPU. VRAM has largely been replaced by the use of SDRAM, "even though it is only single-ported and more overhead is required".

A technique I have used in the past is to use interleaved access to memory. It's a bit complex to explain (the devil is in the details), but I will outline the basics:

Basically the MPU accesses video memory in between pixel accesses by the video-controller. If this timing gets too tight, there are a couple things you can do that will greatly relieve the timing (usually only 1 of these is necessary):

  1. You can use 2 RAM chips (or banks) and interleave those using each chip for every-other pixel. In your case, this would effectively slow your pixel clock to 80ns per chip allowing MPU and video-controller access to have windows of 40ns each. This could be extended to more banks interleaving more pixels if necessary. This technique is called Interleaved Memory.
  2. You can increase the data-bus size of the video memory. The video-controller would read multiple pixels in a single access and use them sequentially. The MPU would either have a larger data-bus, each access would be directed to the appropriate byte (or word) and byte-selects would be used on the video memory, or a read-modify-write would have to be performed to write to the larger data size. In your case, it would probably be simplest to increase the video memory data bus to 16 or 32 bits (2 or 4 pixels), and probably then use an MPU with the same bus size.

If you interleave video accesses, you may want to consider the use of an FPGA or CPLD for your video memory controller.

Another method is to have 2 separate video memories and use bank-select. The MPU writes to one bank while the other is being used by the video-controller for display. When the MPU is finished writing, the bank accesses are swapped (usually during a sync pulse).


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