# Calculating differential PCB traces - Edge-Coupled Microstrip

I finally have the microstrip characteristic impedance thing figured out. But now, of course, I need to learn about differential signalling on PCB traces.

I've spent some time researching. Here is my understanding. Please tell me if I have anything wrong! I have a few specific questions at the end :)

As the two microstrips get closer together their coupling increases, and their ODD characteristic impedance gets smaller. In addition to the "standard" benefits of differential signalling (noise immunity, signal quality, etc), this allows you to use significantly smaller traces than if you were using two non-coupled, single microstrips.

My board has a UWB transceiver in the 6.5 GHz range. Its RF pins are $100\Omega$ differential, which will run to a balun.

My questions:

1. It appears that I should solve for odd characteristic impedances of $50\Omega$ each. Is this true?

2. Using the TNT Field Solver mentioned by @RolfOstergaard, I find that 8.3 mil traces with 5.3 mil space between them (13.6 mil center-to-center) gives me $Z_{odd} = 50.05\Omega$. My board house can do 5/5 mil trace/space. Is there any reason not to use these values?

3. How much of an effect will soldermask have on the circuit? Should I keep the differential traces uncovered?

Thanks! Here's the pcb stackup:

Top: 1-oz copper.
6.7 mil FR-408 prepreg (Er = 3.66 @ 1 GHz).
Ground: 1/2-oz copper.
47 mil FR-408 core.
Power: 1/2-oz copper.
6.7 mil FR-408 prepreg.
Bottom: 1-oz copper.

• Incidentally I get your results when I take the Dk to be 4.2 and trace thickness to be 0.7 mil, which would be 1/2-oz copper. But you say the top layer has 1-oz copper. This will be increased if you have plated through vias, so you might want to calculate with a thickness of 2.1 mil or so instead of 0.7, if that is what you were doing. – The Photon Jul 8 '14 at 21:15
• @ThePhoton Thanks for running the numbers. In this case, with FR-408, the Dk is 3.66. I just ran them again, and the results are similar with 1-oz copper over 3.66(Dk) substrate, or 1/2-oz copper over 4.2 substrate. Interesting :) – bitsmack Jul 8 '14 at 21:32
• @ThePhoton Would you please expand on the copper being thicker with plated through vias? I haven't heard about that before. – bitsmack Jul 8 '14 at 21:33
• The plating doesn't just fill the vias, it also goes on to all the outer layer copper areas. – The Photon Jul 8 '14 at 22:31

It appears that I should solve for odd characteristic impedances of 50 Ohms each. Is this true?

Yes, the differential-mode impedance is equal to twice the odd-mode impedance (at least for symmetric geometries).

My board house can do 5/5 mil trace/space. Is there any reason not to use these values?

If you can fit a design with larger gaps and wider traces, then the differential impedance will be less sensitive to over-etching or under-etching during pcb fabrication.

How much of an effect will soldermask have on the circuit? Should I keep the differential traces uncovered?

Is a fairly small effect. But if you can, it's worth checking the geometry with a simulator that can account for the effect. Your fab shop may be able to do this for you, if they aren't a totally low-cost shop.

Leaving the traces unmasked is also an option. But remember to leave a sliver of solder mask around each component pad to act as a solder dam.

If you are using a higher-end fab shop, you can also simply specify that you want 100-ohm differential traces, and let them adjust the trace width according to their knowledge of the material characteristics, solder mask thickness, trace thickness, etc.