This question is very rudimentary one. Please point me to the link if this question has been already asked.

In general, when working with simulations and and analyzing the standard cells designed based on CMOS logic, a capacitive load is tied to the output of the cell or gate. Why is it not a resistive load but a capacitive one? The timing characteristics are measured after tying the output to a standard capacitive value. Wouldn't the delays measured during the simulations (e.g. using SPICE based tools) be affected due to the rise and fall times of the connected capacitor?

Edit: If the capacitive load seems a realistic option, wouldn't a RC combination be still simple and more realistic?

  • \$\begingroup\$ Maybe that's the whole point - it represents reality \$\endgroup\$ – Andy aka Jul 10 '14 at 10:54
  • \$\begingroup\$ @Andyaka please see the edit \$\endgroup\$ – Raghunath V Jul 10 '14 at 11:05

Capacitors are used as test loads in CMOS logic because the actual load when connected to other logic (the gates of additional MOSFET transistors) is primarily capacitive.

  • \$\begingroup\$ yes. but purely capacitive? Why not an RC combination? \$\endgroup\$ – Raghunath V Jul 10 '14 at 10:59
  • \$\begingroup\$ There is also impedance to be taken into account \$\endgroup\$ – Raghunath V Jul 10 '14 at 11:00
  • \$\begingroup\$ Drain-source resistances of MOSFETs in the gate give the R in RC. \$\endgroup\$ – Szymon Bęczkowski Jul 10 '14 at 15:14
  • \$\begingroup\$ @SzymonBęczkowski: Yes, but that's modeled as part of the gate, not part of the load. \$\endgroup\$ – Dave Tweed Jul 10 '14 at 15:16
  • \$\begingroup\$ Merely, the point still maybe that using a single component might reduce complexity during measurements :/ \$\endgroup\$ – Raghunath V Jul 11 '14 at 4:13

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