This question is very rudimentary one. Please point me to the link if this question has been already asked.
In general, when working with simulations and and analyzing the standard cells designed based on CMOS logic, a capacitive load is tied to the output of the cell or gate. Why is it not a resistive load but a capacitive one? The timing characteristics are measured after tying the output to a standard capacitive value. Wouldn't the delays measured during the simulations (e.g. using SPICE based tools) be affected due to the rise and fall times of the connected capacitor?
Edit: If the capacitive load seems a realistic option, wouldn't a RC combination be still simple and more realistic?