Having little experience with CCD image sensors, I have learned that reading pixels via shift registers from a relatively large size CCD must be fast to achieve some reasonable frame rate. Let's say, for a 5M pixel CCD imager to get a 30fps rate, the pixel readout rate must be at least 150Msps. I thought that running the readout for each row/column separately would be about half of that, but this would require 2.2 thousand pins (for each row, if the imager was square shaped).

So, how does this readout is performed in cameras, smartphones and other devices that provide HD video? Can CDD imagers achieve such high pixel readout rate?


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For CCDs: - It's hard to clock the horizontal shift registers of a CCD much faster than 40 MHz without having a drop in you CTE (Charge transfer efficiency) as there is a limited drift velocity for electrons. The fastest I've even worked with is ~ 45 MHz, and I was cheating. How this problem is solved is to use a "tapped" architecture in which a subset of columns feed a shortened horizontal shift register each being run at the higher rate. So instead of trying to force those outputs out one amplifier you have them come out of 4 or 8 or more.

In your example above that would likely a 4 tap architecture.

I've used sensors that had as many as 256 Taps and an aggregate pixel rate of ~ 10 GPixels/s.

For NON CCD sensors (APS, CIS, APS etc. - how ever you label them) i.e. CMOS image sensor. It's much more easy to run at higher speeds with outputs running at 80 MHz or more. Faster than than become problematic with power and noise levels. So indeed these two end up being tapped.


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