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Say I have a very simple program that functions perfectly fine on a ARM Cortex M0+ processor. How much will I need to change in order for it to work on an ARM Cortex M4 processor, assuming they are both made by the same company and I have imported the new cores header.

I just can't think of any reason it wouldn't work. They use a similar instruction set. I mean the M4 has a much more expanded Thumb-2 instruction set over the M0+. In my experience, companies keep the same naming scheme when they make their ARM device headers.

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  • \$\begingroup\$ Have you tried it? Did it work? \$\endgroup\$
    – Majenko
    Jul 11 '14 at 23:30
  • \$\begingroup\$ I haven't, I actually don't have an M4 arm processor quite yet. \$\endgroup\$
    – Funkyguy
    Jul 11 '14 at 23:31
  • \$\begingroup\$ It should work, but you would be stupid not to recompile and take advantage of the M4 instructions. You could test it in an LPC43xx, which has both an M4 and one or two M0, with access to the same peripherals. \$\endgroup\$
    – starblue
    Jul 12 '14 at 6:32
  • \$\begingroup\$ You don't need to have the hardware on hand to try to compile for it, though if you do the peripheral interfacing directly rather than through a library, you will need the hardware (or an extremely high fidelity simulator) to validate that. \$\endgroup\$
    – Chris Stratton
    Jul 18 '14 at 16:42
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The CPU should not give you any problems, as you say the instruction set of an M4 is a superset of the M0/M0+ instruction set. Note that the timing might be different, so busy-wait based timing might not work the same.

Peripherals can be a PITA, I would not assume they are the same unless the datasheets read the same.

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  • \$\begingroup\$ Thanks! I'm glad to hear that the concepts in programming it will more or less be the same. \$\endgroup\$
    – Funkyguy
    Jul 12 '14 at 22:00
  • \$\begingroup\$ "The Cortex-M0 CPU ... executes a subset of the Thumb-2 instruction set. This enables fully compatible, binary, upward migration of the code to ... the Cortex-M3 and M4." -- PSoC 4000 Family Datasheet \$\endgroup\$
    – davidcary
    Jul 14 '14 at 17:01
  • \$\begingroup\$ Indeed, peripheral interface "style" can be drastically different even between mostly pin-compatible upgrade-path devices from the same vendor. \$\endgroup\$
    – Chris Stratton
    Jul 18 '14 at 16:42
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If your software is in ASM/compiled format it will work (as Cortex M4 is superset of Cortex M0), but it will be suboptimal.

If your software is in C/C++ (essentially it can be recompiled), you will have to choose:

  • compile for M0 (and do not use more powerful instructions),
  • compile for M4 and ensure that other components support it (for example RTOS must save FPU state on context switch context if FPU is used),

Note however that peripherals can be not fully compatible, especially if vendor does not care for such compatibility. Event if vendor care, and your software changes reserved bits from reset values, peripherals may not work as expected.

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