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Hi I am learning verilog and I am trying to find an answer if I have an output of type reg in a main module connected to the inputs of multiple modules, how in verilog would I specify which module I want the signal from the reg output to go to based on some condition.

    module one(a,b)

        input a;
        output b;
        wire a,b;

        //do something
        assign b = some value;

    endmodule



    module two (a,b)

        input a;
        output b;
        wire a,b;

        //do something
        assign b = some value;


    endmodule



    module main(c)

        output c;
        input d;

        reg c;
        reg d;

        one mod1 (.a(c), .b(d));
        two mod2 (.a(c), .b(d));

            always(sens list)
            begin

                if(condition)
                    //send reg value to mod1;
                else
                    //send reg value to mod2;

            end

    endmodule

I would think to have the output of the main module AND'ed with a signal specific to that module that I want to send it to based on some condition, but I am unsure of how to translate that into verilog. Thanks!

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1 Answer 1

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I presume you have your input and output pins in the main module swapped. I also presume that the main module should have both c and d in the definition. I presume you are asking how to assign the outputs of the modules to the d output from the main module. Here is the simplest way to implement that:

wire c;
wire d1;
wire d2;
reg d;

reg select;

one mod1 (.a(c), .b(d1));
two mod2 (.a(c), .b(d2));

always @(*) begin
    if (select) begin
        d <= d1;
    end else begin
        d <= d2;
    end
end

Change the always statement to a clocked always statement if you want to register the output.

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