In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think it's important that it is precise. thanks!

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    \$\begingroup\$ Depending on the platform you might have some onboard PLLs that should do the trick. \$\endgroup\$ – Vladimir Cravero Jul 14 '14 at 12:47
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    \$\begingroup\$ Use a PLL to divide by 5 then multiply by 4. \$\endgroup\$ – Majenko Jul 14 '14 at 12:51
  • \$\begingroup\$ Anyway you should really be a bit more specific about your design goals: the two clock domains need to be synchronous? What VGA signal are we talking about? Why 40MHz? \$\endgroup\$ – Vladimir Cravero Jul 14 '14 at 15:31
  • \$\begingroup\$ This is a duplicate of generating 40 MHz clock from 50 MHz in VHDL on stackoverflow. \$\endgroup\$ – user8352 Jul 14 '14 at 18:29
  • \$\begingroup\$ yes it's the same person because someone wrote in here there might more answers \$\endgroup\$ – Ege Jul 15 '14 at 5:54

You need something like this. However, the device must have a VCO in order for this to work.

The circuit works by changing the frequency of a voltage controlled oscillator (VCO) based on the phase difference of two clock signals. The first signal of the two, \$F_I\$ in the diagram, is the reference signal and in the case of a PLL it is generated by dividing the main oscillator's output by an integer value. If the gain of the feedback loop \$N\$ was to be unity, the control voltage of the VCO would change appropriately until the output of the VCO exactly matched the reference input. In order to get an integer multiple of the reference clock signal as the output, all that needs to be done is to divide the signal fed back by that exact integer.


So, in order to get 40MHz from a 50MHz oscillator, the 50MHz signal first needs to be divided by 5. This 10MHz signal will be the PLL reference signal (\$F_I = 10MHz\$). This now needs to be multiplied by 4 and so by selecting \$N = 4\$, the output of the PLL will be \$F_O = 40MHz\$.

If the FPGA device you are using doesn't have embedded PLLs, you can use a ADPLL (all digital PLL).

Here are a few application notes:

Silicon Labs intro to ADPLLs

Xilinx DPLL reference design

  • \$\begingroup\$ @thebok: You mention this is for generating a VGA signal. I just had a look at some code I had that did exactly that from 5 years ago, and I managed to generate a VGA (640x480) signal with a 25MHz clock. \$\endgroup\$ – Evan Jul 14 '14 at 14:58
  • \$\begingroup\$ yes but for different resolutions you need different clock speeds, my case is here tinyvga.com/vga-timing/800x600@60Hz \$\endgroup\$ – Ege Jul 15 '14 at 5:56

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