Porting my answer from SO. Which focuses on why it is impractical to synthesise absolute delays
When synthesising clock trees the synthesis tool balances these by adding delays so that all nodes receive the clock at the same time, so it would seem that the synthesis tool does have the ability to add delays.
However when ASICs are manufactured there is a variance in speed, at a high level this can be viewed as Slow, Typical and Fast. In practice there are hundreds of variations of these corners where certain types of device in the silicon run fast and others slow.
These corners of the silicon also have a temperature rating, worst case may be +140C Fast silicon and -40C Slow silicon. The variation of the delay through a buffer in this case could be from 1ns to say 30ns.
To bring this back to Verilog if
#10 was synthesisable you would actually get 155+-145 ie 10ns to 300ns, if you have also designed something with
#20 to be part of the same interface or control structure it is going to have a range of 20ns to 600ns. Therefore the whole thing is not really valid against your design. You do not get the exact
#20 that were specified.
The clock trees are designed in a way to cap the max and min delays and so that all nodes on the clock tree will scale relative to each other. They are never given such a strict rule that it must be #10ns as this is physically impossible to guarantee in a combinatorial circuit.