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If I want to read a (bunch of) 74HC165 chip(s) over an SPI port on a microcontroller, this is simple enough. Connect them through Q7 to DS on each, apply the final Q7 to MISO, notCE to SS and CP to SCK. This works fine.

But now how do I share the SPI bus with other devices that I want to read? The 165's Q7 output is never hi-Z, so I can't share the MISO pin with other devices. I'd need some way to "detach" it - a buffer of some kind.

I know there are 74-series chips that have various buffers that can be made hi-Z (such as a 74HS240) but that's a whole additional chip just to be able to share the shift register. Perhaps some cunning way to put a transistor between the final Q7 and the microcontroller's MISO, controlled by the SS line?


Edit: Alternatively, can someone suggest some other parallel-in serial-out shift register that does have a tristate serial output line, and therefore suitable to use on an SPI bus?

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    \$\begingroup\$ Why not us a real SPI chip, like an MCP23S08 or MCP23S17? \$\endgroup\$ – Wouter van Ooijen Jul 15 '14 at 9:04
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    \$\begingroup\$ One reason is because 165's are cheap and available from many sources. The designed-for-SPI chips lock you into a single vendor. (On the other hand, since I work for Microchip, by all means, please buy our parts. :-) \$\endgroup\$ – Jason S Jul 15 '14 at 16:43
  • \$\begingroup\$ Indeed - the 165s are dirt-cheap and I can get them in packs of five from Amazon. One reason I want to use them is for external device IO - if I blow one up accidentally I can easily and cheaply replace it. Less so for a more expensive and rarer chip \$\endgroup\$ – LeoNerd Jul 15 '14 at 23:15
  • \$\begingroup\$ I have made like you said in the past (just simulation). A BJT as the chip-select, on the Q7. A BC549 will work great depending on the speed of the SPI bus. The problem with this approach is that it will be open-drain, so depending on speed you could use a resistor like has said. \$\endgroup\$ – Diego C Nascimento Jul 15 '14 at 23:16
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can someone suggest some other parallel-in serial-out shift register that does have a tristate serial output line, and therefore suitable to use on an SPI bus?

Mouser, Newark, and a few other distributors and suppliers have a selection filter that helps when I'm looking for "something like a 74HC165, but with tristate serial output":

74HC589: 8-bit serial or parallel input; serial output; shift register with 3-state output. "The HC589A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs."

-- On Semiconductor datasheet; Fairchild datasheet (So it meets the "must have a second source" criteria that some projects have, as mentioned by Jason S).

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  • \$\begingroup\$ Aha - the '589 looks just right in that case; similar to a 165 but with tristate output indeed. Just what I was looking for. Thanks. \$\endgroup\$ – LeoNerd Sep 8 '14 at 22:13
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As you noted, the 165 is not a 'full' SPI device because it doesn't tri-state its output.

If you have a single 165 on your SPI bus and speed is not a big issue you could place a resistor (10k?) between the 165 output and the uC MISO pin. Other SPI chips (that do tri-state their output) will override the weak drive through the resistor, but without other chips active the weak drive will prevail, but you might need to slow the clock down (for the 165 only).

If you have multiple 165's you could use a multiplexer chip (151). This costs extra select lines for the mux chip, but you can share the 165's notCE lines (which otherwise would have been separate), and use one of the inputs for the 'real' SPI chips.

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  • \$\begingroup\$ The 151 doesn't appear to have an output enable line either, so that just moves the problem. At this point I'd have to put all my devices' MISO lines through the 151 chip, and now I have to drive both its multiplexer lines -and- the SS lines of the SPI devices, using more pins on the uC. This surely defeats the entire purpose of the shared MISO/MOSI/SCK bus. \$\endgroup\$ – LeoNerd Jul 15 '14 at 7:10
  • \$\begingroup\$ When you have multiple 165's you save a notCE line for each 165, at the cost of N select lines for 2^N-1 165's. (the -1 being the 'real' SPI devices). \$\endgroup\$ – Wouter van Ooijen Jul 15 '14 at 9:01
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The 74xx125 and '126 are quad buffers with tri-state outputs, individually controlled - you could use one package to buffer four 165s...

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  • \$\begingroup\$ Well the point of the SPI chain is not to need four individual 165s connected to the uC directly; I can make them all in one long chain. So I'd only need a single tristate buffer. \$\endgroup\$ – LeoNerd Jul 15 '14 at 7:03
  • \$\begingroup\$ @LeoNerd this has not to do with SPI, its just based on application. Having it chain implicates that you need to update the hole chain for a single change. For high responsiveness/speed applications and/or low-frequency SPI bus, or even to reduce EMI, having each 74xx125 as a slave is better, and better. \$\endgroup\$ – Diego C Nascimento Jul 15 '14 at 23:07
  • \$\begingroup\$ I've recently discovered you can get "one gate" versions of the 74'125 and '126 chips; e.g. see SN74AHC1G125. I've ordered myself a bunch of these, as those seem ideal for isolating never-hi-Z serial output lines of these chips to put them on a true SPI bus. \$\endgroup\$ – LeoNerd Jan 14 '15 at 14:55
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You described how you can cascade a bunch of 74HC165 chips into a long chain. A bunch of the 74HC595 chips also can be cascaded together into a similar daisy-chain.

One way to "share the SPI bus with other devices" is to chain all your chips into one long SPI daisy chain. It's been a while since I did it, but I seem to remember that I could put 74HC165 chips, 74HC595 chips, and similar chips into one long loop. No matter how many chips were in the daisy chain loop, or what order they were in, I only required 4 pins on the microcontroller.

The microprocessor MOSI pin drives the MOSI pin of the first chip in the chain, each chip is cascaded so its serial output drives the serial input of the next chip in the chain, and the MISO pin of the last chip in the chain drives the MISO pin of the microprocessor.

The microprocessor clocks in / clocks out a full loop's worth of data every time it want to change any output or read any input.

That's how JTAG works, right?

Such a long daisy-chain loop is slower, but requires fewer pins on the microcontroller than the "Independent slave SPI configuration". Unfortunately, some chips that claim to support SPI cannot be daisy-chained.

The whole reason you are even considering SPI is because you are running out of pins on the microcontroller and you are connected to something that doesn't need high speeds, right?

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