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I attached an LTspice schematic, a very simplified version of a MOSFET half-bridge driven by a push-pull isolated signal transformer. The FETs are cross-conducting, but their gate pulses are not overlapped. If I am getting things wrong, can someone please show me the error, why are they cross-conducting?

The schematic, as seen from within LTspice, looks like this (the schematic, in LTspice .asc code, is below):

The schematic in LTspice

Even if the load and the output filter look very strange for the working conditions, they are a test and, if this problem is eliminated, they may as well have the final values as they are, so please ignore them (unless they are culprits).

Some things I have tried:

  • giving up the signal transformer and using brute G-sources (with parallel resistances), while making sure there is no cross conducting driving pulse (which it isn't, even now)

  • increasing the already existent dead-time from 50ns (switching frequency is 400kHz) to 200ns or more, also making sure there are no cross-conducting driving pulses

  • using lower Vcc (from 300V to 30V) and using 6nC/6mOhms NXP FET (from default database), while making sure the two previous changes fit the needs (no cross-conducting gate drive, etc). This change, for example, shows the FETs conducting while the gate pulses go negative(!!!).

I might add other minor things such as removing Cpar from the supplies, leaving only Rser, or adding ideal diodes to gate-source with ".model d d Vrev=12" (an ideal Zener), etc.

After all these changes I still get cross-conducting even though there is a considerable gap between the gate pulses. Sometimes (see change #3) I get both FETs conducting when it's impossible for them to conduct (but that may be because I used 30V FETs on a 30V rail; testing, nothing else). At this point I decided to ask for help.

Here's the LTspice schematic


Version 4
SHEET 1 2260 680
WIRE 1712 -192 1552 -192
WIRE 1552 -160 1552 -192
WIRE 928 -128 736 -128
WIRE 1104 -128 928 -128
WIRE 1376 -112 1344 -112
WIRE 1456 -112 1440 -112
WIRE 1456 -80 1456 -112
WIRE 1488 -80 1456 -80
WIRE 1504 -80 1488 -80
WIRE 1344 -64 1344 -112
WIRE 1344 -64 1328 -64
WIRE 1408 -64 1344 -64
WIRE 928 -16 928 -48
WIRE 976 -16 928 -16
WIRE 1104 -16 1104 -48
WIRE 1152 -16 1104 -16
WIRE 864 0 816 0
WIRE 880 0 864 0
WIRE 1056 0 1024 0
WIRE 752 16 672 16
WIRE 1456 16 1328 16
WIRE 1552 16 1552 -64
WIRE 1552 16 1456 16
WIRE 1632 16 1552 16
WIRE 1664 16 1632 16
WIRE 1776 16 1744 16
WIRE 1792 16 1776 16
WIRE 1552 32 1552 16
WIRE 1792 32 1792 16
WIRE 672 48 672 16
WIRE 1376 80 1344 80
WIRE 1456 80 1440 80
WIRE 1456 112 1456 80
WIRE 1488 112 1456 112
WIRE 1504 112 1488 112
WIRE 1344 128 1344 80
WIRE 1344 128 1328 128
WIRE 1408 128 1344 128
WIRE 1024 160 1024 0
WIRE 816 176 816 32
WIRE 1024 176 1024 160
WIRE 1024 176 816 176
WIRE 1456 208 1328 208
WIRE 1536 208 1456 208
WIRE 1552 208 1552 128
WIRE 1552 208 1536 208
FLAG 1792 96 0
FLAG 1776 16 out
FLAG 1632 16 x
FLAG 1712 -112 0
FLAG 1552 288 0
FLAG 1552 -192 +
FLAG 1536 208 -
FLAG 880 48 0
FLAG 1056 48 0
FLAG 736 -48 0
FLAG 1104 64 0
FLAG 928 64 0
FLAG 1488 -80 g1
FLAG 1488 112 g2
FLAG 864 0 c
FLAG 1024 160 _c
FLAG 672 128 0
SYMBOL cap 1776 32 R0
SYMATTR InstName Cf
SYMATTR Value 50p Rser=100k Cpar=680p
SYMATTR SpiceLine Rpar=1Meg
SYMBOL ind2 1648 32 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName Lf
SYMATTR Value 30m
SYMATTR Type ind
SYMATTR SpiceLine Rser=100m Rpar=1e6
SYMBOL voltage 1712 -208 R0
WINDOW 3 27 90 Left 2
SYMATTR Value 300 rser=.1 cpar=100u
SYMATTR InstName V3
SYMBOL voltage 1552 304 M180
WINDOW 3 24 16 Left 2
WINDOW 0 24 96 Left 2
SYMATTR Value 300 rser=.1 cpar=100u
SYMATTR InstName V5
SYMBOL ind2 912 -32 M180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName La1
SYMATTR Value {Lc}
SYMATTR Type ind
SYMATTR SpiceLine Rser=1 Rpar=10k
SYMBOL ind2 1088 -144 R0
SYMATTR InstName La2
SYMATTR Value {Lc}
SYMATTR Type ind
SYMATTR SpiceLine Rser=1 Rpar=10k
SYMBOL ind2 1344 32 R180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName Lb1
SYMATTR Value {Lc} rser=27
SYMATTR Type ind
SYMATTR SpiceLine Rpar=10k
SYMBOL ind2 1344 112 M0
SYMATTR InstName Lb2
SYMATTR Value {Lc} rser=27
SYMATTR Type ind
SYMATTR SpiceLine Rpar=10k
SYMBOL sw 928 80 M180
SYMATTR InstName S1
SYMBOL sw 1104 80 M180
SYMATTR InstName S2
SYMBOL voltage 736 -144 R0
WINDOW 3 23 91 Left 2
SYMATTR Value 12 rser=10
SYMATTR InstName V1
SYMBOL voltage 672 32 R0
WINDOW 3 23 91 Left 2
SYMATTR Value pulse 0 1 0 0 0 2u 2.5u
SYMATTR InstName V4
SYMBOL nmos 1504 -160 R0
SYMATTR InstName M1
SYMATTR Value STP8NM60
SYMBOL Digital\\buf 752 -48 R0
WINDOW 123 -12 140 Left 2
SYMATTR Value2 trise=500n tfall=1n
SYMATTR InstName A1
SYMBOL pmos 1408 16 M180
SYMATTR InstName M3
SYMATTR Value ZXM62P02E6
SYMBOL schottky 1376 -96 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value BAT54
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL schottky 1376 96 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D2
SYMATTR Value BAT54
SYMATTR Description Diode
SYMATTR Type diode
SYMBOL pmos 1408 208 M180
SYMATTR InstName M4
SYMATTR Value ZXM62P02E6
SYMBOL nmos 1504 32 R0
SYMATTR InstName M2
SYMATTR Value STP8NM60
TEXT 760 296 Left 2 !.tran 0 50u 0 startup
TEXT 752 336 Left 2 !.opt plotwinsize=0
TEXT 912 -160 Left 2 !k1 la1 lb1 la2 lb2 1
TEXT 912 -200 Left 2 !.model sw sw ron=7 roff=10meg vt=0.5 vh=0
TEXT 760 256 Left 2 !.param Lc=10m

Anticipated thanks, Vlad

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  • \$\begingroup\$ How about a schematic rather than a bunch of statements? \$\endgroup\$ – Andy aka Jul 15 '14 at 13:44
  • \$\begingroup\$ The code block is the schematic. Copy-paste it in your favourite text editor and save it as an *.asc file to open it with LTspice. Since I was asking for help with a schematic for LTspice, I thought people would recognize the format and the "Version 4" header. \$\endgroup\$ – Vlad Jul 15 '14 at 14:15
  • \$\begingroup\$ I'm aware of what the code block is. If you feel the problem is an LTSpice thing then OK, good luck. If the problem isn't an LTSpice thing then not posting a circuit is restricting your answers but you know best. \$\endgroup\$ – Andy aka Jul 15 '14 at 14:26
  • \$\begingroup\$ I don't know where the problem is, LTspice or my approach, but whatever the case, I'm stuck and I'm asking for help by providing the schematic with the problem that came up when using LTspice. That is, the problem and the tool with which it has occurred. I don't understand what other schematic are you referring to because, as I said, this is a simplified (read idealistic) version; ideal meaning the problem should really not be happening. You say that you are aware of what the code block means, were you curious to see what schematic I have given? \$\endgroup\$ – Vlad Jul 15 '14 at 15:16
  • \$\begingroup\$ Andy's saying, you should add a schematic image to your question if you want people to begin to spend time on this question. You obviously already have it in image form, why make people jump through hoops (open it in their own schematic editor) when you've already done the work? Leave the LTSpice code up as well if someone wants to really dive deep into your problem after they've determined there's no problem with the image schematic. \$\endgroup\$ – horta Jul 15 '14 at 15:24
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Are you sure you want two NMOS's to do this? It would be much simpler if you used a PMOS. Otherwise, it's not terribly surprising you're getting cross conduction since Vgs depends on the source voltage as well as the gate voltage. Even if the gate pulse goes negative, if the source voltage on the top MOSFET goes even lower than that, then you'll still get conduction when you didn't want it to.

If you want to stick with two NMOS's then you'll need to ensure that the gate voltage of the top NMOS stays at the source voltage if you want it off. You may want to add plots to this question showing Vg and Vs of both MOSFETs so that we can make a more concise answer.

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  • \$\begingroup\$ I think there's no need now, you are right. The problem is the output filter with 30mH, V(x) wasn't dropping fast enough. The default values were 30uH and 680nF, but the currents would have been far too big for a kOhm load, so I thought I'd increase Lf for that, ignoring the downside. Still, I'd like to keep the high value to lower current consumption, is there a way to force V(x) to go low with V(g1,x)? \$\endgroup\$ – Vlad Jul 15 '14 at 16:39
  • \$\begingroup\$ @Vlad it's not a good idea to try and force V(x). Instead what you want to do is force V(g1) to depend on V(x). That can be done using various methods using schottkey diodes or resistors and capacitors. If you don't understand that though, you would probably be better using a PMOS which wouldn't have this dependancy at all. \$\endgroup\$ – horta Jul 15 '14 at 17:22
  • \$\begingroup\$ The schematic, as mentioned, is a simplified version of the final one, which had proper driving, feedback, snubbers, etc, but which also showed cross-conducting (not as much, though). Now I understand I also overlooked Coss and, since the snubbers didn't do the job, I thought I'd ask about a different approach (whatever works), PMOS is not a choice (inherent mismatches). Understanding is never a problem, overlooking is, unfortunately, and that's my mistake, but, surely there's no need for presumptions. My purpose is to make it work, not to go blindly by the book, so I'll do anything it takes. \$\endgroup\$ – Vlad Jul 16 '14 at 6:55
  • \$\begingroup\$ @Vlad Andy's just upset that you didn't put pictures to begin. And it'd be difficult to get to the conclusion you did without pictures of waveforms as well. I'm glad you figured out your problem, but I'm not sure I should get much credit for helping. \$\endgroup\$ – horta Jul 16 '14 at 13:43
  • \$\begingroup\$ Your answer got me on the right track, so I see it only fair to be so. Thank you. As for the schematic vs pictures, I am mostly used with a different group where it is better (and required) to upload your schematic (& dependencies) because then the user(s) can run the simulation and see exactly what the problem is. That way you have all the details you need. Otherwise there's the risk of answering based on theory and assumptions instead of facts, but that's just me. The minor downside here is that I had to copy-paste the contents of the .asc file, which is not a pretty sight, true. \$\endgroup\$ – Vlad Jul 16 '14 at 15:57

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