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I've placed a KSZ9031MNX Ethernet PHY on my board, and am now trying to get power routed to it. The digital side will merely be annoying to do, I think, but I'm at a complete loss on the analog side.

Pins vs Bypass Capacitors

The analog supply pins are placed between the inner and outer signal pairs and I have no real good idea where to place those capacitors (except for the backside, which I'd like to avoid as these would be the only components there).

I've highlighted the positive supply pins and the corresponding pads on the capacitors I plan to use. The differential pairs going to the magnetics should be fairly obvious; I think these will have to be moved around a bit still.

My first attempt looks like this:

Bypass Capacitor Placement Attempt

The traces on the bottom layer routing the power to the vias are still missing, but I think that might work.

Is it a good idea to have the capacitors bridge the differential traces to save space, or will that have negative effects on signal quality?

Should I try to keep the ground plane between the differential pairs, should I connect that area to analog ground to give the analog ground connection in the middle more copper, or is that irrelevant?

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  • \$\begingroup\$ It looks like you have some legitimate questions, but it's hard to tell what that layout picture is supposed to tell us. We can't tell which nets are what, and with all the writing over everything, it would be hard to follow anyway. You wouldn't hand in a mess like this for homework, so it doesn't belong here either. \$\endgroup\$ – Olin Lathrop Jul 15 '14 at 20:35
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    \$\begingroup\$ It looks like you are using broadside-coupled diff pairs? (Instead of side-by-side). Interesting; I do not see that technique used often. \$\endgroup\$ – dext0rb Jul 16 '14 at 1:16
  • \$\begingroup\$ I've cleaned up the picture a bit and made the airwires more visible -- the interesting network is the highlighted one, with four pins on the IC. \$\endgroup\$ – Simon Richter Jul 16 '14 at 1:25
  • \$\begingroup\$ My rationale for doing the differential pairs like this was that it would allow me to keep more distance between pairs -- this way, I get about .5mm, while routing them in parallel would leave .3mm only (and I have to swap two of the pairs anyway). \$\endgroup\$ – Simon Richter Jul 16 '14 at 1:39
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imo, you did it completely wrong. because:

what you did in both cases? you traced one wire within each pair on one side of the board while other wire on the another side. ascii-graphically it looks like so:

   a+  b+  c+  d+ 
   ==  ==  ==  ==
-------------------- top side
-------------------- bottom side
   ==  ==  ==  ==
   a-  b-  c-  d-

but any case you must keep both wires of a pair on single layer and when you change the layer for one wire in the pair you must do the same for the last wire as close as possible the first one.

in your case if you have less space, you can trace two pairs on the top layer and two pairs on the bottom one, like this:

  a+  a-    c+  c- 
  ==  ==    ==  ==
-------------------- top side
-------------------- bottom side
  ==  ==    ==  ==
  b+  b-    d+  d-

i shown no internal layers, but if you have those, you must route all the pairs over the analog ground plane/polygon. in other guidlines, follow the micrel's recommendation given in the appropriate application note(s).

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