# Verilog: is connection without wires possible?

I am sorry to ask this question, which I believe is very basic, but I cannot find an answer. The following example clearly works. But I would like to omit the declaration of the wires ay and by.

module sub(output reg y);
endmodule

module top(input wire sel,output wire x);
wire ay,by;

sub a(.y(ay));
sub b(.y(by));

assign x= sel ?ay:by;

endmodule


Modules have a names. It is possible to address their ports directly? if yes, what is the correct syntax? This does not work (in Quartus)

module sub(output reg y);
endmodule

module top(input wire sel,output wire x);

sub a();
sub b();

assign x= sel ?a.y:b.y;

endmodule


No, it's not possible to do this.

The module.wire syntax works in some systems, but all the synthesis tools will require you to use the ports properly.

• thank you. what are the instance names used for then? just for reports? Jul 16 '14 at 10:41
• They're used whenever you need to identify a particular instance, such as in SDC constraints. They get used when exporting to other file formats too. Jul 16 '14 at 11:18

Wire declarations can be omitted and in most case a 1 bit wide wire will be implied. This is generally considered bad practise as you will end up with width mismatches if you forget to declare those wider than 1 bit.

module sub(output reg y);
endmodule

module top(input wire sel,output wire x);
//wire ay,by; No wire declaration

sub a(.y(ay)); //1 bit wide wire implied
sub b(.y(by));

assign x= sel ?ay:by;

endmodule


Unconnected outputs will be optimised away by synthesis.

• thank you, however my purpose was omitting the connection in the module instantation. Jul 16 '14 at 10:42
• Why would you want to do that? any way no you can not and would lead to really bad programming practise. Verilog describes hardware and how it is connected. Jul 16 '14 at 11:22
• for the same reason that if you have a struct in c you can access its members by structName.member Jul 16 '14 at 15:22
• but your describing hardware and connectivity not just functionality. Unless your talking about verification of a design then you have different approaches. Jul 16 '14 at 17:26