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This question already has an answer here:

In VHDL how can I get a clock frequency of 40 MHz if my onboard clock is 50 MHz. I know how to divide the frequency by integers but this case is dividing by 1.25. I am using this for VGA so I think it's important that it is precise. thanks!

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marked as duplicate by placeholder, Vladimir Cravero, Matt Young, Chetan Bhargava, Dave Tweed Jul 16 '14 at 21:23

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  • \$\begingroup\$ cross posting should be punished with hours of justin bieber \$\endgroup\$ – Vladimir Cravero Jul 16 '14 at 16:08
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It depends on the capabilities of your specific FPGA, but for Xilinx parts at least, you can use an MMCM or PLL to multiply the clock up, then divide it back down. For example, you might multiply by 20 then divide by 25. Xilinx coregen can generate paramaters for an MMCM or PLL that match the VCO bandwidth capabilities if you give it your input clock speed and desired output speed. If you're using an Altera (or other) brand of FPGA, they will have some kind of similar clock manipulation unit, but I don't know what they are called.

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