Is 'IF' statement necessary for the clock process?

Question

I'm used to writing the following process that will react on the rising edge of the CLK (script 1):

X: PROCESS(CLK)
BEGIN
    IF RISING_EDGE(CLK) THEN OUTPUT <= CLK AND VAR;
    ELSE NULL;
    END IF;
END PROCESS X;

Now I need the process to react on both rising and falling edges of CLK, so according to the device datasheet I wrote this (script 2):

X: PROCESS(CLK)
   BEGIN
        IF (CLK'EVENT) THEN OUTPUT <= CLK AND VAR;
        ELSE NULL;
        END IF;
END PROCESS X;

Both cases fit and can be programmed on the device. But it seems like the second case does not really work: the OUTPUT does not change.

I need the OUTPUT to be updated on both edges of the CLK. Would it be functionally equivalent to script 2 if I rewrite the process as the following (script 3)? In other words, do I have to put IF condition, or the process reacts on the rising/falling edge of the CLK regardless?

X: PROCESS(CLK)
   BEGIN
      OUTPUT <= CLK AND VAR;
END PROCESS X;

EDIT: With script 2 I get the warning that the signal VAR is missing from the sensitivity list. However, I need the OUTPUT to change only with CLK, but be dependent on VAR value.

With Script 4 (below), which I would expect to be equivalent to script 2, the warning is different: WARNING:Xst:2110 - Clock of register OUTPUT seems to be also used in the data or control logic of that element.

X: PROCESS(CLK)
   BEGIN
       IF (CLK'EVENT) THEN
           IF CLK = '1' THEN OUTPUT <= ('1' AND VAR);
           ELSE OUTPUT <= '0';
           END IF;
       ELSE NULL;
       END IF;
END PROCESS X;

Here's the fitter report with relevant vars(NICLK is for OUTPUT and SampEn is for VAR):

Answer 1

A concurrent signal assignment statement of the form:

OUTPUT <= CLK AND VAR;

Has an equivalent process (how it's simulated) of the form:

process
begin
   OUTPUT <= CLK AND VAR;
   wait on CLK, VAR;  -- wait on 'sensitivity list'
end process;

With the wait statement the equivalent of putting both right hand side signals in a sensitivity list.

The second process is already sensitive to CLK events, the if CLK'EVENT is redundant. I'd suggest that your synthesis tool should likely have generated a warning and may have not produced an assignment to OUTPUT, something examining synthesis warnings, any produced net list or generated schematic might indicate. Otherwise the second and third processes are equivalent.

You're likely to get warning for both the second and third process statements that VAR is missing from the sensitivity list, which is likely ignored for synthesis purposes. The effect of this is not have closure between simulation results pre- and post-synthesis.

Note that what you've defined is a gated clock and having VAR in the sensitivity list won't matter unless VAR transitions before the rising edge of CLK or after the falling edge of CLK, in which case it could move the OUTPUT clock edge (if OUTPUT'EVENT and OUTPUT = '1', if rising_edge(OUTPUT), or the same for the falling edge).

And if VAR could screw up your resulting 'clock' edge you have a problem that should be addressed anyway.

(And of course someone is bound to chime in that a sensitivity list can use the reserved word all to signify all right hand side signals in VHDL-2008).

addendum

The questioner has indicated he's trying to gate clocks, and from added information to his question shows this is using Xilinx tools.

Xilinx recommends against gating clocks this way [1], the most obvious reason is that clock skew becomes dependent on routing to and from a LUT as well as the the LUT delay itself. You could imagine trying to balance delays in all your clocks. With clocks generated from a higher clock rate you could for instance disable a clock with a clear or reset. The idea here is match delays on gated and non gated clocks as an FPGA implementation issue above and beyond all the measures you'd take to cross clock boundaries otherwise.

Xilinx supports gated clocks in series 7 FPGAs and ZYNQ devices using dedicated clock enables through the use of the paid version of ISE (Vivaldo), something called intelligent clock gating, where you don't gate your clocks, you let the tools do it for you.

You could also note the period constraint is lost passing through an non-sequential element manually gating clocks.

---

[1] White Paper: HDL Coding Practices to Accelerate Design Performance, around Figure 11. Starting on Page 10, Clock Enable and Gated Clocks.

Answer 2

The common way to do clock gating for an output clock is to use a DDR output buffer, with the data_h signal connected to the gate signal and data_l connected to '0', and the clock connected normally.

The main reason for that is that the LEs do not really have adequate circuitry for this task. The FFs in the LEs can only update on the rising edge of a clock, and the LUTs cannot hold state without a latch, which has some stability issues.

Internally, you could create the signal you want from within a LUT if you have a shifted clock (e.g. 90 degrees), but the output would need to be shunted over to a clock network to be useful, and it would be too jittery to be a good clock.

So if you need a gated clock internally, you'd transmit the "enable" signal along with the clock, and synthesis would feed those into the "enable" input of the affected FFs.